DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 13A, Claims 1-20) in the reply filed on 07/01/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 12-14, 17 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Kim et al. (US 2020/0303479 A1).
Regarding Claim 1, Kim (Fig. 4, 5) discloses a display panel comprising:
a base layer (110);
a circuit layer (112, 113, 114, T1, Cst) disposed on the base layer (110) and including a plurality of pixel pattern units (T1, Cst) arranged in a first direction and a second direction intersecting the first direction (See Fig. 4, 1st direction and second direction);
a valley (area between T1, Cst) defined between the plurality of pixel pattern units (T1, Cst); and
a filler disposed (organic filler 161) in the valley (area between T1, CS2), wherein
each of the plurality of pixel pattern units (T1, Cst) includes at least one semiconductor layer (ES) and at least one conductive layer (CS2), and wherein
a portion of a side surface of the valley is defined by at least one layer among the at least one semiconductor layer and the at least one conductive layer. (“the etch stop layer ES may include a semiconductor material or a metal”, Cst)
Regarding Claim 2, Kim (Fig. 4, 5) discloses the display panel of claim 1, wherein
the at least one layer (ES) is in direct contact with the filler (131).
Regarding Claim 3, Kim (Fig. 4, 5) discloses the display panel of claim 1, wherein
the filler is an organic material. (organic filler 161).
Regarding Claim 6, Kim discloses the display panel of claim 1, wherein
the valley includes a first valley extending in the first direction and a second valley extending in the second direction intersecting the first direction. (See area between T1, CS2 in Fig. 4)
Regarding Claim 12, Kim (Fig. 4, 5) discloses the display panel comprising:
a base layer (110);
a circuit layer (ES, CST, 111) including at least one semiconductor layer (ES), at least one conductive layer (CST), and at least one inorganic insulating layer (111);
a light emission element layer (OLED) disposed on the circuit layer (ES, CST, 111); and
an encapsulation layer (420, 430) disposed on the light emission element layer (OLED), wherein
a valley (area between T1, CS2) formed by removing a portion of the at least one inorganic insulating layer (111) is defined in the circuit layer, and wherein
a portion of a side surface of the valley (area between T1, CS2) is defined by at least one layer among the at least one semiconductor layer (ES) and the at least one conductive layer (CST).
Further, limitation in line 2, “a valley formed by removing a portion of the at least one inorganic insulating layer” is considered to be product-by-process.
“Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding Claim 13, Kim (Fig. 4, 5) discloses the display panel of claim 12, further comprising:
an organic material (organic filler 161), wherein
the valley is filled with the organic material (organic filler 161).
Regarding Claim 14, Kim (Fig. 4, 5) discloses the display panel of claim 13, wherein
the at least one layer (ES) is in direct contact with the organic material (161).
Regarding Claim 17, Kim discloses the display panel of claim 12, wherein t
the valley includes a plurality of first valleys, and a plurality of second valleys intersecting the plurality of first valleys, wherein
each of the plurality of first valleys extends in a first direction and the plurality of first valleys are spaced apart from each other in a second direction intersecting the first direction, and each of the plurality of second valleys extends in the second direction and the plurality of second valleys are spaced apart from each other in the first direction. (See grid of valleys intersecting 1st direction and second direction in Fig. 4)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 7, 15, 16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200303479 A1) in view of Park et al. (US 2019/0267440 A1)
Regarding Claim 4, Kim (Fig. 4, 5) discloses the display panel of claim 1, wherein
Kim does not explicitly disclose that a portion of a bottom surface of the valley is defined by any one layer among the at least one semiconductor layer and the at least one conductive layer.
Park (Fig. 15) discloses a portion of a bottom surface of a valley (area between T1, C2) is defined by any one layer (C2) among the at least one semiconductor layer and the at least one conductive layer. (C2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Park such that a portion of a bottom surface of the valley is defined by any one layer among the at least one semiconductor layer and the at least one conductive layer in order to reduce a probability that a crack propagation through the inorganic insulating layer and provide a flat upper surface, a probability of defect occurrence may be drastically reduced in manufacturing the horizontal and vertical connection wires [0102-0104]
Regarding Claim 5, Kim in view of Park discloses the display panel of claim 4, wherein
the any one layer (C2, Park) is in direct contact with the filler. (161, Park)
Regarding Claim 7, Kim discloses the display panel of claim 1, wherein
each of the plurality of pixel pattern units (T1, CS2) includes
Kim does not explicitly disclose a first sub-pixel pattern unit and a second sub-pixel pattern unit that is line-symmetrical to the first sub-pixel pattern unit.
Park (Fig. 16, 17) discloses a first sub-pixel pattern unit (PC1) and a second sub-pixel pattern unit (PC2) that is line-symmetrical to a first sub-pixel pattern unit. (Fig. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Park such that a first sub-pixel pattern unit and a second sub-pixel pattern unit that is line-symmetrical to the first sub-pixel pattern unit in order to valley to surround grouped sub-pixels [0212-0213].
Regarding Claim 15, Kim (Fig. 4, 5) discloses the display panel of claim 13.
Kim does not explicitly disclose a portion of a bottom surface of the valley is defined by any one layer among the at least one semiconductor layer and the at least one conductive layer.
Park (Fig. 15) discloses a portion of a bottom surface of a valley (area between T1, C2) is defined by any one layer (C2) among the at least one semiconductor layer and the at least one conductive layer. (C2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Park such that a portion of a bottom surface of the valley is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer in order to reduce a probability that a crack propagation through the inorganic insulating layer and provide a flat upper surface, a probability of defect occurrence may be drastically reduced in manufacturing the horizontal and vertical connection wires [0102-0104]
Regarding Claim 16, Kim in view of Park discloses the display panel of claim 15, wherein
the any one layer (Park C2) is in direct contact with the organic material (“first organic planarization layer 161” Park).
Regarding Claim 18, Kim (Fig. 4, 5) discloses display panel comprising:
a base layer (110);
a circuit layer (112, 113, 114 ,T1, Cst)) disposed on the base layer ( and including a plurality of pixel pattern units (T1, Cst) arranged in a first direction and a second direction intersecting the first direction and a plurality of inorganic insulating layers (112, 113, 114) (See Fig. 4, 1st direction and second direction);
a valley (area between T1, Cst) defined by removing portions of the plurality of inorganic insulating layers (112, 113, 114) between the plurality of pixel pattern units (T1, Cst); and
a filler (organic filler 161) disposed in the valley and including an organic material (organic filler 161), wherein
each of the plurality of pixel pattern units (T1, Cst) includes at least one semiconductor layer (ES) and at least one conductive layer (Cst2), and wherein
the at least one semiconductor layer (ES) exposed by the valley ((area between T1, Cst) is in direct contact with the filler (161).
Kim does not explicitly disclose that the at least one conductive layer exposed by the valley is in direct contact with the filler
Park (Fig. 15) discloses at least one conductive layer (C2) exposed by a valley area between T1, C2) is in direct contact with a filler (organic filler 161).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Park such that the at least one conductive layer exposed by the valley is in direct contact with the filler in order to reduce a probability that a crack propagation through the inorganic insulating layer and provide a flat upper surface, a probability of defect occurrence may be drastically reduced in manufacturing the horizontal and vertical connection wires [0102-0104]
Further, limitation in line 2, “a valley defined by removing portions of the plurality of inorganic insulating layers” is considered to be product-by-process.
“Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding Claim 19, Kim in view of Park discloses the display panel of claim 18, wherein
the valley includes a first valley extending in the first direction and a second valley extending in the second direction intersecting the first direction. (See grid of valleys intersecting 1st direction and second direction in Fig. 4)
Regarding Claim 20, Kim in view of Park discloses the display panel of claim 18.
Kim in view of Park as previously combined does not explicitly disclose each of the plurality of pixel pattern units includes a first sub-pixel pattern unit and a second sub-pixel pattern unit that is line-symmetrical to the first sub-pixel pattern unit.
However, Park (Fig. 16, 17) discloses a first sub-pixel pattern unit (PC1) and a second sub-pixel pattern unit (PC2) that is line-symmetrical to a first sub-pixel pattern unit. (Fig. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Park such that a first sub-pixel pattern unit and a second sub-pixel pattern unit that is line-symmetrical to the first sub-pixel pattern unit in order to valley to surround grouped sub-pixels [0212-0213].
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200303479 A1) in view of Son et al. (US 2018/0366586 A1).
Regarding Claim 8, Kim discloses the display panel of claim 1, wherein
the circuit layer includes:
a first semiconductor layer (S1) disposed on the base layer (110);
a first insulating layer (112) configured to cover the first semiconductor layer (S1);
a first conductive layer (G1) disposed on the first insulating layer; (112)
a second insulating layer (113) configured to cover the first conductive layer (G1);
a second conductive layer (Cst2) disposed on the second insulating layer;
a third insulating layer (114) configured to cover the second conductive layer;
the first insulating layer (112), the second insulating layer (113), the third insulating layer (114) include an inorganic material. [0089]
Kim does not explicitly disclose a second semiconductor layer disposed on the third insulating layer;
a fourth insulating layer configured to cover the second semiconductor layer;
a third conductive layer disposed on the fourth insulating layer; and
a fifth insulating layer configured to cover the third conductive layer, and wherein
the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer include an inorganic material.
Son (Fig. 3) discloses a second semiconductor layer (221) disposed on a third insulating layer (114);
a fourth insulating layer (115) configured to cover the second semiconductor layer;
a third conductive layer (225S) disposed on the fourth insulating layer; and
a fifth insulating layer (116) configured to cover the third conductive layer, and wherein
the fourth insulating layer (115), and the fifth insulating layer (116) include an inorganic material. [0055, 0060, 0071]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Son such that a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer configured to cover the second semiconductor layer; a third conductive layer disposed on the fourth insulating layer; and a fifth insulating layer configured to cover the third conductive layer, and wherein the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer include an inorganic material in order to have a second TFT that performs various functions such as compensation and initialization in the driving circuit. [0055, 0060]
Regarding Claim 9, Kim in view of Son discloses the display panel of claim 8, wherein
the valley (H1 Son) is provided by removing at least portions of the first insulating layer (112 Son, Kim), the second insulating layer (113 Son, Kim), the third insulating layer (114 Son, Kim), the fourth insulating layer, and the fifth insulating layer (116 Son).
Regarding Claim 10, Kim in view of Son discloses the display panel of claim 8, wherein
the portion of the side surface of the valley (H1 Son) (area between T1, Cst Kim) is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer. (Fig.4, 5 Kim) (Fig. 3 Son)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200303479 A1) in view of Son et al. (US 2018/0366586 A1) and further in view of Park et al. (US 2019/0267440 A1).
Regarding Claim 11, Kim in view of Son discloses the display panel of claim 8, wherein
Kim in view of Son a portion of a bottom surface of the valley is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer.
Park (Fig. 15) discloses a portion of a bottom surface of a valley (area between T1, C2) is defined by a third conductive layer (C2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel in Kim in view of Son and Park such that a portion of a bottom surface of the valley is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer in order to reduce a probability that a crack propagation through the inorganic insulating layer and provide a flat upper surface, a probability of defect occurrence may be drastically reduced in manufacturing the horizontal and vertical connection wires [0102-0104]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2022/0093705 A1) discloses valley filled with organic material.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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