DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I, claims 1-16 and 21-24, in the reply filed on June 12, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on January 15, 2024, January 22, 2025 and May 22, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first set of die connectors have different widths than the second set of die connectors” (claim 7); “the first set of die connectors are wider than the second set of die connectors” (claim 9); and “active devices” (claim 12) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “the width W2 is larger than the width W1”, “the width W2 is smaller than the width W1”, “the width W4 is larger than the width W3”, and “the width W4 is smaller than the width W3” as described in the specification ([0052]). Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “24” ([0025] filed 8/14/24), “410” ([0083]) and “504” ([0096]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “74” (Fig. 5). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: i) “3 through 12B should read :3-11, 12A and 12B” ([0021]) and ii) undefined acronyms/symbols, such as “FR4” (first occurrence: [0083]). The examiner suggests that applicant spell out all the acronyms/symbols when using them for the first time in the disclosure.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-16 and 21-24 are objected to because of the following informalities: a comma should be inserted after “method” (claims 1, 12 and 21, line 1) and after claim number (claims 2, 3 and 14, line 1). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There appears to be no adequate description in the specification for the claim limitation of “forming a … redistribution structure over the …”, as recited in claims 1 and 12; and “forming conductive features over a carrier substrate”, as recited in claim 10.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “the first”, as recited in claim 1 (last line), 5, 6, 12 and 16, is unclear as to the first of which element applicant refers.
The claimed limitation of “second sets of die connectors”, as recited in claim 1, last line, is unclear as to whether said limitation is the same as or different from “a second set of die connectors”, as recited in claim 1, line 12.
The claimed limitation of “second dielectric layers”, as recited in claims 5 and 6, is unclear as to whether said limitation is the same as or different from “a second dielectric layer”, as recited in claim 3.
The claimed limitation of “the sidewalls of …”, as recited in claim 7, is unclear as to the sidewalls of which element applicant refers.
The claimed limitation of “the first set of die connectors are wider than the second set of die connectors”, as recited in claim 9, is unclear as to what of the first set of die connectors are wider than what of the second set of die connectors applicant refers.
Claim 10 recites the limitation “the bonded first and second dies” in lines 3 and 5. There is insufficient antecedent basis for this limitation in the claim.
The claimed limitation of “second sets of conductive vias”, as recited in claim 12, last line, is unclear as to whether said limitation is the same as or different from “a second set of die connectors”, as recited in claim 12 (line 18).
Claim 10 recites the limitation “the bonded first and second integrated circuit dies” in lines 3 and 5. There is insufficient antecedent basis for this limitation in the claim.
The claimed limitation of “second encapsulants”, as recited in claim 16, is unclear as to whether said limitation is the same as or different from “a second encapsulant”, as recited in claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (2020/0402942).
As for claim 1, Chen et al. show in Figs. 1-3 (or4), 5-14 and related text a method comprising:
forming a first die 100A (Figs. 1-8), the forming comprising:
forming through vias 136 in a first substrate 131;
forming a first redistribution structure 132 (132a/132b) over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias;
forming a first set of die connectors 133/134 over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate (Fig. 1);
thinning a second side of the first substrate, the thinning exposing the through vias (Fig. 3 or 4);
bonding the first die to a second die 200 (Fig. 9);
encapsulating the first die with a first encapsulant 140m (Fig. 11); and
forming a second set of die connectors 164 over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors (Fig. 13).
As for claim 2, Chen et al. show forming a first dielectric layer 135 on the first set of die connectors and the first redistribution structure, the first dielectric layer having sidewalls coterminous with sidewalls of the first redistribution structure, the first set of die connectors being in the first dielectric layer (Figs. 1, 9 and 14).
As for claim 3, Chen et al. show forming a second dielectric layer 162 on the first set of die connectors, the first dielectric layer, and the first encapsulant, the second set of die connectors being in the second dielectric layer (Fig. 13).
As for claim 4, Chen et al. show the second dielectric layer has sidewalls coterminous with sidewalls of the first encapsulant (Fig. 14).
As for claim 5, Chen et al. show the first and second dielectric layers are polymer layers ([0032], [0065]-[0066]).
As for claim 6, Chen et al. show the first and second dielectric layers comprise different materials ([0032], [0066]).
As for claim 7, Chen et al. show the first encapsulant contacts the sidewalls of the first dielectric layer and the first redistribution structure (Fig. 14).
As for claim 8, Chen et al. show the first set of die connectors have different widths than the second set of die connectors (Fig. 14).
As for claim 9, Chen et al. show the first set of die connectors are wider than the second set of die connectors (arbitrarily chosen: Fig. 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (2020/0402942) in view of Yu et al. (2020/0381391).
Chen et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except forming conductive features over a carrier substrate; attaching the bonded first and second dies to the carrier substrate adjacent the conductive features; encapsulating the bonded first and second dies and the conductive features in a second encapsulant; and forming a second redistribution structure over the bonded first and second dies, the conductive features, and the second encapsulant, the second redistribution structure being electrically coupled to the second set of die connectors and the conductive features.
Yu et al. teach in Figs. 7-17 and related text forming conductive features 78 over a carrier substrate 60 (Fig. 7);
attaching the bonded first and second dies 54 (22/42) to the carrier substrate adjacent the conductive features (Fig. 8);
encapsulating the bonded first and second dies and the conductive features in a second encapsulant 80 (Fig. 9); and
forming a second redistribution structure 82/86/88/90/92/94/96 over the bonded first and second dies, the conductive features, and the second encapsulant.
Chen et al. and Yu et al. are analogous art because they are directed to a method of forming a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. with the specified feature(s) of Yu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form conductive features over a carrier substrate; attach the bonded first and second dies to the carrier substrate adjacent the conductive features; encapsulate the bonded first and second dies and the conductive features in a second encapsulant; and form a second redistribution structure over the bonded first and second dies, the conductive features, and the second encapsulant, as taught by Yu et al., in order to form a fan-out package, to reduce the cost and the size of the device.
Therefore, the combined device shows the second redistribution structure being electrically coupled to the second set of die connectors and the conductive features.
30. Claim(s) 11, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (2020/0402942) and Yu et al. (2020/0381391) in view of Yu et al. (2018/0269188, hereinafter Yu’188).
Chen et al. and Yu et al. disclosed substantially the entire claimed invention, as applied to claim 10 above, including forming conductive connectors 112 over and electrically coupled to the second redistribution structure (Yu: Fig. 17);
removing the carrier substrate (Yu: Fig. 14).
Chen et al. and Yu et al. do not disclose bonding the conductive connectors to a package substrate.
Yu’188 teaches in Figs. 19-21 and related text bonding the conductive connectors 166 to a package substrate 400.
Chen et al., Yu et al. and Yu’188 are analogous art because they are directed to a method of forming a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. and Yu et al. with the specified feature(s) of Yu’188 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to bond the conductive connectors to a package substrate, in order to provide a high level of integration and component density.
Claim(s) 12-15, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (2020/0365557) in view of Chen et al. (2020/0402942).
Tsai et al. show in Figs. 2A-2D, 9, 7B-7E, and related text:
As for claim 12, a method comprising:
encapsulating a first integrated circuit die 110 (1101-1104) in a first encapsulant 120 (Fig. 2B), the first integrated circuit die comprising a first substrate (not shown) and active devices (not show) ([0029-0030]);
forming a first redistribution structure 130 over the first integrated circuit die and the first encapsulant (Fig. 2C);
forming a second integrated circuit die 140 comprising a second substrate (not shown) and active devices (not shown), forming the second integrated circuit die comprising:
forming through vias 148 in the second substrate (Fig. 5A);
forming a second redistribution structure 146 to over the through vias and the second substrate, the second redistribution structure being electrically coupled to the through vias (Fig. 2D);
forming a first set of conductive vias 1461 over and electrically coupled to the second redistribution structure, the first set of conductive vias being on a first side of the second substrate (Fig. 5A);
bonding the first integrated circuit die to the second integrated circuit die (Figs. 2D and 9);
encapsulating the second integrated circuit die with a second encapsulant 120a(120) (Figs. 7B and 9); and
forming a second set of conductive vias (mover and electrically coupled to the first set of conductive vias (via of) 150, the first and second sets of conductive vias forming stacked conductive vias (Fig. 7C and 9).
As for claim 13, forming a first dielectric layer 147 on the first set of conductive vias and the second redistribution structure, the first dielectric layer having sidewalls coterminous with sidewalls of the second redistribution structure, the first set of conductive vias being in the first dielectric layer.
Tsai et al. do not disclose forming the second integrated circuit die comprising: thinning a second side of the second substrate, the thinning exposing the through vias (claim 12); the first dielectric layer is a first polymer layer (claim 13).
Chen et al. teach in Figs. 1-3 (or 4), 5-14 and related text:
As for claim 12, forming a second integrated circuit die 100A comprising a second substrate 131 and active devices (not shown, [0021]), forming the second integrated circuit die comprising:
forming through vias 136/137 in the second substrate (Fig. 1);
forming a second redistribution structure 132 (132a/132b) over the through vias and the second substrate, the second redistribution structure being electrically coupled to the through vias (Fig. 1);
forming a first set of conductive vias 133/134 over and electrically coupled to the second redistribution structure, the first set of conductive vias being on a first side of the second substrate (Fig. 1);
thinning a second side of the second substrate, the thinning exposing the through vias (Fig. 3 or 4).
As for claim 13, forming a first polymer layer 135 on the first set of conductive vias 133/134 and the second redistribution structure 132, the first polymer layer having sidewalls coterminous with sidewalls of the second redistribution structure, the first set of conductive vias being in the first polymer layer (Fig. 8).
Tsai et al. and Chen et al. are analogous art because they are directed to a method of forming a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tsai et al. with the specified feature(s) of Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to thin a second side of the second substrate, the thinning exposing the through vias, and use polymer, as a first dielectric layer, as taught by Chen et al., in Tsai et al.'s device, in order to reduce electrical resistance and capacitance, reduce package thickness, exposes the TSVs and improve the performance of the device.
As for claim 14, the combined device shows forming a second polymer layer on the first set of conductive vias, the first polymer layer, and the second encapsulant, the second set of conductive vias being in the second polymer layer (Tsai: Fig. 7C; [0060], [0032]).
As for claim 15, the combined device shows the second polymer layer has sidewalls coterminous with sidewalls of the second encapsulant (Tsai: Fig. 7C).
Claim(s) 16, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (2020/0365557) and Chen et al. (2020/0402942) in view of Yu et al. (2020/0381391).
Tsai et al. and Chen et al. disclosed substantially the entire claimed invention, as applied to claim 12 above, except forming conductive features over a carrier substrate; attaching the bonded first and second integrated circuit dies to the carrier substrate adjacent the conductive features; encapsulating the bonded first and second integrated circuit dies and the conductive features in a third encapsulant, the third encapsulant contacting the first and second encapsulants; and forming a third redistribution structure over the second integrated circuit die, the conductive features, and the third encapsulant, the third redistribution structure being electrically coupled to the second set of conductive vias and the conductive features.
Yu et al. teach in Figs. 7-17 and related text forming conductive features 78 over a carrier substrate 60 (Fig. 7);
attaching the bonded first integrated circuit and second integrated circuit dies 54 (22/42) to the carrier substrate adjacent the conductive features (Fig. 8);
encapsulating the bonded first integrated circuit and second integrated circuit dies and the conductive features in a third encapsulant 80 (Fig. 9); and
forming a third redistribution structure 82/86/88/90/92/94/96 over the second integrated circuit die, the conductive features, and the third encapsulant.
Tsai et al., Chen et al. and Yu et al. are analogous art because they are directed to a method of forming a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tsai et al. and Chen et al. with the specified feature(s) of Yu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form conductive features over a carrier substrate; attach the bonded first integrated circuit and second integrated circuit dies to the carrier substrate adjacent the conductive features; encapsulate the bonded first integrated circuit and second integrated circuit dies and the conductive features in a third encapsulant; and form a third redistribution structure over the second integrated circuit die, the conductive features, and the second encapsulant, as taught by Yu et al., in order to form a fan-out package, to reduce the cost and the size of the device.
Therefore, the combined device shows the third encapsulant contacting the first and second encapsulants; and
the second redistribution structure being electrically coupled to the second set of die connectors and the conductive features.
Claim(s) 21-24, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (2018/0269188) in view of Yu et al. (2020/0381391, hereinafter Yu’391).
As for claim 21, Yu et al. show in Figs. 30, 31, 3-6, 32-35 method comprising:
forming a back-side redistribution structure 1001/1004/1005/1002 over a carrier substrate 100 (Fig. 30);
forming through vias 112 extending away from the back-side redistribution structure, the through vias being electrically coupled to the back-side redistribution structure (Fig. 30);
adhering a package component (package structure) to the back-side redistribution structure, the package component comprising a first die and a second die ([0126]), the package component further comprising stacked die connectors 126 (Fig.31);
encapsulating the through vias and the package component with an encapsulant 130 (Fig. 32);
forming a front-side redistribution structure 160 over the encapsulant, the through vias, and the package component, the front-side redistribution structure being electrically coupled to the through vias and the stacked die connectors (Figs. 4 and 33);
forming first conductive connectors 166 over and electrically coupled to the front-side redistribution structure (Figs. 5 and 33);
removing the carrier substrate (Fig. 6 and 33); and
forming second conductive connectors 1014 extending through the back-side redistribution structure and electrically coupled to the back-side redistribution structure (Fig. 34).
Yu et al. do not explicitly disclose the package component comprising the first die bonded to the second die.
Yu’391 teaches in Figs. 4-17 and related text the package component 54 comprising the first die 40 bonded to the second die 42.
Yu et al. and Yu’391 are analogous art because they are directed to a method of forming a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu et al. with the specified feature(s) of Yu’391 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the package component comprising the first die bonded to the second die, as taught by Yu’391, in Yu et al.’s device, in order to minimize the system operational speed restrictions, reduce the cost and the size of the device.
As for claim 22, the combined device shows adhering the package component comprises adhering a back-side of the package component to the back-side redistribution structure with a die attach film 1010 (Yu: Fig. 31; [0127]).
As for claim 23, the combined device shows coupling an upper package component 300 to the second conductive connectors, the upper package component comprising a memory die 308A encapsulated by a molding material 312 (Yu: [0051]; [0054]).
As for claim 24, the combined device shows mounting the front-side redistribution structure to a package substrate 400 with the first conductive connectors, an underfill (not shown) being between the front-side redistribution structure and the package substrate and surrounding the first conductive connectors ([0065]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MEIYA LI/Primary Examiner, Art Unit 2811
Prosecution Insights