DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/10/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The phrase “comprises a plurality of dielectric layers arranged in an array” in claim 1 is a relative term which renders the claim indefinite. The phrase “comprises a plurality of dielectric layers arranged in an array” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In this instant case, the invention claims the contact gate structure comprises a plurality of dielectric layers arranged in an array from the top view renders the claim indefinite because the relationship between the contact gate structure and the columnar dielectric pillars is unclear. For instance, figure 11 shows the dielectric columns surround the contact gate structure, and figure 12 shows that the entire contact gate structure includes the columnar dielectric layers. The specification states the contact gate structure composes slot contact structures but does not provide clarity for ascertaining the orientation of the contact gate structure being comprised of columnar dielectric layers in claim 1. One ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For the purposes of this action, the claim will be interpreted to mean the contact gate structure comprises columnar dielectric layers (fig 2: IL) surrounding the gate electrode (fig 2: GE1).
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-6 and 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsuiki et. al. (PG Pub. US 20160056233 A1).
Regarding claim 1, Mitsuiki teaches a semiconductor structure (¶0008, fig 2: transistor for use in a semiconductor device) comprising:
a substrate (¶0050, fig 2:SUB) defining a high-voltage device region (¶0098, fig 2: ANR region is 10V) wherein the substrate of the high-voltage device region comprises a first region (annotated fig 2: first region), a first groove surrounding the first region (annotated fig 2: first region), and a second region surrounding the first groove (annotated fig 2: groove 1); and
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a contact gate structure (fig 2: composition of GE1/ IL) located in the high-voltage device region, wherein the contact gate structure (fig 6a: composition of 70,72, and 44) comprises a plurality of columnar dielectric layers (annotated fig 2: dielectric columns) arranged in an array from a top view (annotated fig 2: dielectric columns are in an array of 2 dielectric columns arranged in one row, extending the x-direction).
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Regarding claim 2, Mitsuiki teaches the semiconductor structure according to claim 1, wherein the first region (annotated fig 2: first region) of the substrate has a first surface (annotated fig 2:annotated fig 2: first surface) and the second region of the substrate has a second surface (annotated fig 2: second surface), the first surface is lower than the second surface, and the material of the first region (annotated fig 2: first region) is the same as the material of the second region (fig 2: second surface and first surface are included on the SUB).
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Regarding claim 3, Mitsuiki teaches the semiconductor structure according to claim 2, further comprising an insulating layer (¶0048, fig 2: GI1 insulating film) covering the substrate (¶0048, fig 2: SUB) (fig 2: GI1 covers SUB).
Regarding claim 4, Mitsuiki teaches the semiconductor structure according to claim 3, wherein the contact gate structure (fig 2: composition of GE1/ IL) is located on the insulating layer (¶0048, fig 2: GI1) and above the first region (annotated fig 2: first region).
Regarding claim 5, Mitsuiki teaches the semiconductor structure according to claim 3, further comprising a dielectric layer (¶0057, fig 2: IL, an insulating layer in a transistor is a dielectric layer) located on the insulating layer (¶0048, fig 2: GI1).
Regarding claim 6, Mitsuiki teaches the semiconductor structure according to claim 5, further comprising a slot contact structure (¶0057, fig 2: CT1) located in the dielectric layer (¶0057, fig 2: IL) and directly contacting the second surface (annotated fig 2: second surface), of the second region.
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Regarding claim 9, Mitsuiki teaches the semiconductor structure according to claim 2, wherein a bottom surface of the first groove (annotated fig 2: bottom part of groove 1) is lower than the first surface (annotated fig 2: first surface).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuiki as applied to claim 6 above, and further in view of Kwon (PG Pub. US 20160240542 A1, hereinafter ‘Kwon’).
Regarding claim 7, Mitsuiki teaches the semiconductor structure according to claim 6, including the contact gate structure (fig 2: composition of GE1/ IL) and the slot contact structure (¶0057, fig 2: CT1)
Mitsuiki does not teach the contact gate structure and slot contact structures are made of a same metal material.
Kwon teaches the contact gate structure (fig 1: composition of 173 and 120) and slot contact structures (¶0047: fig 1: 171 and 172) are made of the same metal material (¶0056, fig 1: 173/120 and 171/172 are made of metal, and therefore comprise the same material type).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to make the contact gate structure and slot contact structures in Mitsuiki with the same metal material as in Kwon to simplify manufacturing processes.
Regarding claim 8, Mitsuiki in view of Kwon teaches the semiconductor structure according to claim 7, wherein the dielectric layer (Mitsuiki ¶0057, fig 2: IL) directly contacts the metal material of the contact gate structure (Mitsuiki fig 2:GE1/IL) (IL directly contacts GE1 on the top).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LYTESHIA M PRICE/ Examiner, Art Unit 2818
/BRIAN TURNER/ Primary Examiner, Art Unit 2818
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