Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 12th, 2024 was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: In paragraph 0025, line 3, “tan electrically conductive layer” should read “electrically conductive layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation " a hardness" in lines 1 and 2. The hardness could be referring to either material magnetic hardness, or another unspecified definition of the term. The limitation will be interpreted as any form of “material hardness”.
Claim 19 recites the limitation " a hardness" in lines 1 and 2. The hardness could be referring to either material magnetic hardness, or another unspecified definition of hardness, with no specified unit of measurement. The limitation will be interpreted as “material hardness”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Reznicek et al. (US 2021/0159390 A1; hereinafter Reznicek).
Regarding claim 11, Reznicek teaches a manufacturing method of a semiconductor device (Fig. 1-9: memory device 100; [0023]), comprising:
forming magnetic tunnel junction (MTJ) structures (Fig. 5-9: MTJ pillar 510) above a substrate (Fig. 1-9: substrate 108); and
forming a write structure (Fig. 8 and 9: 820) on the magnetic tunnel junction structures, wherein the write structure is connected with the magnetic tunnel junction structures (Fig. 8 and 9: 820 contacting the bottom surface of 510), and the write structure comprises:
spin-orbit torque (SOT) patterns separated from one another (Fig. 8 and 9: 304), wherein each of the spin-orbit torque patterns is disposed on and connected with one of the magnetic tunnel junction structures (Fig. 8 and 9: 304 connected to 510); and
an electrically conductive layer covering the spin-orbit torque patterns (Fig. 8 and 9: conductive material 804; [0041]), wherein the electrically conductive layer is partly disposed above the spin-orbit torque patterns in a vertical direction (Fig. 8: 804 surrounding 304 from above) and partly disposed between the spin-orbit torque patterns in a first horizontal direction (Fig. 8: 804 disposed on the left and right of 304 and between MTJ pillars 510).
Regarding claim 12, Reznicek teaches the manufacturing method of the semiconductor device according to claim 11, wherein a method of forming the write structure comprises:
forming a dielectric layer on the substrate (Fig. 4-9: hard mask layer 420; [0033], “may include dielectric material”), wherein
the dielectric layer covers the magnetic tunnel junction structures (Fig. 5-9: MTJ pillar covered on the top by 420);
forming a first trench in the dielectric layer, wherein the first trench exposes each of the magnetic tunnel junction structures (Fig. 4-5 and 6-7: trench formed exposing the MTJ pillars in figures 4-5 and recesses 730 formed in figure 7; [0040]);
forming the spin-orbit torque patterns in the first trench (Fig. 7: 304 formed in the trench); and
forming the electrically conductive layer in the first trench (Fig. 8: 804 formed in the trench).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komura et al. (US 2022/0006006 A1; hereinafter Komura).
Regarding claim 1, Komura discloses a semiconductor device (Fig. 1 and 5: 100), comprising:
a substrate (Fig. 1: substrate 10);
magnetic tunnel junction (MTJ) structure (Fig. 1: tunnel magnetoresistance (TMR) element 20; [0056]) disposed above the substrate.
and a write structure (Fig. 1 and 5: spin-orbit torque wiring 40) disposed on and connected with the magnetic tunnel junction structure (Fig. 1: 40 disposed on 20), wherein the write structure comprises:
spin-orbit torque (SOT) patterns (Fig. 5: spin current generation part 41; [0118]) separated from one another, wherein the spin-orbit torque pattern is disposed on and connected with one of the magnetic tunnel junction structures (Fig. 5: 41 disposed on layer 24 of 20); and
an electrically conductive layer (Fig. 5: low resistance parts 42a, 42b, and 42c) covering the spin-orbit torque patterns, wherein the electrically conductive layer is partly disposed above the spin-orbit torque patterns in a vertical direction (Fig. 5: 42C disposed vertically from 41) and partly disposed between the spin-orbit torque patterns in a first horizontal direction (Fig. 5: 41 sandwiched between 42a and 42b; [0118]).
Komura fails to explicitly teach a plurality of MTJ structures, and a plurality of SOT patterns. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate the MTJ and corresponding SOT patterns disclosed in Fig. 1 and 5 of Komura an array structure in order to increase data storage capacity. The resulting array structure would include a plurality of MTJ structures and a plurality of SOT patterns.
Regarding claim 2, Komura teaches the semiconductor device according to claim 1, wherein each of the magnetic tunnel junction structures comprises:
a free layer (Fig. 1 and 5: ferromagnetic metal layer 23; [0057]); and
a spin-orbit torque layer (Fig. 1 and 5: cap layer 24; [0069] – [0072], stated to require spin conductivity for spin transfer from the spin-orbit torque wiring) disposed above the free layer (Fig. 5: 24 above 23), wherein
each of the spin-orbit torque patterns is connected with the spin-orbit torque layer of the magnetic tunnel junction structure disposed under the spin-orbit torque pattern (Fig. 5: 41 and 24 connected through junction 24’; [0118]).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Komura, as applied to claim 2 above, and in further view of Lee et al. (US 2020/0083429 A1; hereinafter Lee).
Regarding claim 3, Komura does not explicitly teach the semiconductor device according to claim 2, wherein a material composition of the spin-orbit torque patterns is different from a material composition of the spin-orbit torque layers.
However, Lee teaches a material composition of the spin-orbit torque patterns (Fig. 2a: conductive patterns 130; [0055] – [0057]) is different from a material composition of the spin-orbit torque layers (Fig. 2a: conductive patterns 130; [0058], “conductive patterns 130 may include a material different from conductive patterns 150”).
It would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention to use the materials of Lee in the embodiment of Komura in order to have different materialistic properties, such as resistivity, required by each of the SOT patterns and SOT layers.
Regarding claim 4, Komura does not explicitly teach, the semiconductor device according to claim 2, wherein a hardness of each of the spin-orbit torque patterns is lower than a hardness of each of the spin-orbit torque layers.
However, applicant discloses in paragraph [0023] of the Specification, hafnium (Hf), rhenium (Re), ruthenium (Ru) may be used for the SOT layers has increased hardness from tungsten (W), gold (Au) and tantalum (Ta) which may be used for the SOT patterns. Lee discloses the same materials disclosed as applicant in an SOT pattern and SOT layers ([0054] – [0058], conductive line SOL includes conductive patterns 130 and 150 stated to be made from a list of materials which discloses hafnium (Hf), rhenium (Re), ruthenium (Ru), tungsten (W), gold (Au), and tantalum (Ta) etc.). Because these materials disclose by Lee are the same as the materials disclosed by applicant, it would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention that these same materials would exhibit the same claimed properties (ie. a hardness of the spin torque layer being greater than the hardness of the spin torque pattern).
Regarding claim 5, Komura does not explicitly teach, the semiconductor device according to claim 2, wherein electrical resistivity of each of the spin-orbit torque patterns is lower than electrical resistivity of each of the spin-orbit torque layers.
However, applicant discloses in paragraph [0023], tungsten (W), gold (Au), and tantalum (Ta) which may be used for the SOT patterns has lower resistivity from hafnium (Hf), rhenium (Re), ruthenium (Ru) may be used for the SOT layers. However, Lee discloses the same materials disclosed as applicant in an SOT pattern and SOT layers ([0054] – [0058], conductive line SOL includes conductive patterns 130 and 150 stated to be made from a list of materials which discloses hafnium (Hf), rhenium (Re), ruthenium (Ru), tungsten (W), gold (Au), and tantalum (Ta) etc.) . Because these materials disclose by Lee are the same as the materials disclosed by applicant, it would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention that these same materials would exhibit the same claimed properties (ie. a resistivity of the spin torque pattern being lower than the resistivity of the spin torque layer).
Regarding claim 6, Komura does not explicitly teach the semiconductor device according to claim 1, further comprising: a dielectric layer disposed above the substrate, wherein the write structure is disposed in the dielectric layer and elongated in the first horizontal direction, and the magnetic tunnel junction structures are arranged in the first horizontal direction.
However, Lee teaches a dielectric layer disposed above the substrate (Fig. 1 and 2: insulating layer 170), wherein the write structure is disposed in the dielectric layer and elongated in the first horizontal direction (Fig. 1 and 2: write structure 130 and 150 shown extending in the D1 direction), and the magnetic tunnel junction structures are arranged in the first horizontal direction (Fig. 1: top-down view shows MTJ structure disposed in a horizontal direction D1).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Komura with the dielectric encapsulation of Lee in order to effectively insulate the MTJ structures between each other without interfering with their respective magnetic fields.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Komura in view of Lee, as applied to claim 6 above, and in further view of Dutta et al. (US 2023/0098576 A1; hereinafter Dutta 1).
Regarding claim 7, Komura and Lee do not explicitly teach the semiconductor device according to claim 6, wherein the write structure further comprises: a barrier layer disposed between the electrically conductive layer and each of the spin-orbit torque patterns, wherein a part of the barrier layer is sandwiched between one of the spin-orbit torque patterns and the dielectric layer in a second horizontal direction orthogonal to the first horizontal direction.
However, Dutta 1 teaches wherein the write structure (Fig. 6: 155) further comprises: a barrier layer (Fig. 6: barrier layer 115; [0056] and [0053]) disposed between the electrically conductive layer (Fig. 6: upper contact 153) and each of the spin-orbit torque patterns (Fig. 6: lower contact 143), wherein a part of the barrier layer is sandwiched between one of the spin-orbit torque patterns and the dielectric layer in a second horizontal direction orthogonal to the first horizontal direction (Fig. 6: sandwiched between dielectric 141 and 143; [0056]).
It would have been obvious to one of ordinary skill in the art to combine the embodiment of Komura in view of Lee with the barrier layers of Dutta 1 in order to prevent diffusion and degradation between the conductive layer and the dielectric layer.
PNG
media_image1.png
815
708
media_image1.png
Greyscale
Annotated Fig. 5 - Komura
Regarding claim 8, Komura teaches the semiconductor device according to claim 7, wherein
the write structure comprises first portions and second portions alternately arranged in the first horizontal direction (see annotated Fig. 5: Everything disposed on 42c is the first portion, and everything to the sides where 42a and 42b reside are the second portions),
each of the first portions consists of one of the spin-orbit torque patterns (see annotated Fig. 5a: spin current generation part 41), the barrier layer disposed above the spin-orbit torque pattern, and the electrically conductive layer disposed above the spin-orbit torque pattern (Fig. 5: 42c above 41), and
each of the second portions consists of a part of the barrier layer located between the spin-orbit torque patterns in the first horizontal direction and a part of the electrically conductive layer located between the spin-orbit torque patterns in the first horizontal direction.
Dutta 1 discloses the following claim limitations not disclosed in Komura:
the barrier layer disposed above the spin-orbit torque pattern (Fig. 6: barrier 115; [0063], upper contact 153 had conductive barrier layers lining the bottom surface which is disposed above 143),
each of the second portions consists of a part of the barrier layer located between the spin-orbit torque patterns in the first horizontal direction and a part of the electrically conductive layer located between the spin-orbit torque patterns in the first horizontal direction (Fig. 6: second portions shown in the in-between area of the lower contact part 143, with the barrier layer 115 lining the sides of the 153 and 143).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Komura in view of Lee with the barrier layer of Dutta 1, to form a barrier layer in the first and second regions separating the MTJ structures in order to prevent diffusion between the conductive layer, the SOT patterns, and the dielectric layer.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Komura in view of Lee as applied to claim 6 above, and in further view of Lin et al. (US 2023/0380293 A1; hereinafter Lin).
Regarding claim 9, Komura and Lee do not explicitly teach the semiconductor device according to claim 6, wherein the dielectric layer comprises:
a first layer; and
a second layer disposed on the first layer, wherein
the write structure is partly disposed in the first layer and partly disposed in the second layer, and
a dielectric constant of the second layer is lower than a dielectric constant of the first layer.
However, Lin teaches wherein the dielectric layer (Fig. 8: dielectric layers 602 and 601) comprises:
a first layer (Fig. 8: cap dielectric layer 601); and
a second layer disposed on the first layer (Fig. 8: dielectric layer 602),
wherein the write structure (Fig. 8: conductive features 702; [0048] may be word lines or bit lines, or the like) is partly disposed in the first layer and partly disposed in the second layer (Fig. 8; [0048], conductive features 702 penetrate through the dielectric portions and both 601 and 602 surround 702 in the horizontal direction), and
a dielectric constant of the second layer is lower than a dielectric constant of the first layer ([0046] and [0047], dielectric layer 601 is formed of a standard dielectric silicon nitride, silicon oxynitride, or the like, and dielectric layer 602 may be formed of a low-k dielectric material).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Komura in view of Lee with the dielectric layers of Lin in order to utilize the properties of the layer of lower dielectric constant to reduce signal interference in the write structure, while maintaining the magnetic field of the MTJ structure in the layer with the higher dielectric constant.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Komura as applied to claim 1 above, and in further view of Sato et al. (US 2020/0006424 A1; hereinafter Sato).
Regarding claim 10, Komura does not explicitly teach the semiconductor device according to claim 1, further comprises:
a first electrode and a second electrode,
wherein the first electrode and the second electrode are disposed on and connected with the write structure, and
the first electrode and the second electrode are located above two opposite ends of the write structure in the first horizontal direction, respectively.
Sato teaches
a first electrode and a second electrode (Fig. 9: 928 and 930 respectively),
wherein the first electrode and the second electrode are disposed on and connected with the write structure (Fig. 9: electrode 114, with interconnect line segments 116, and 118; [0046], include a spin orbit torque material), and
the first electrode and the second electrode are located above two opposite ends of the write structure in the first horizontal direction, respectively (Fig. 9: 928 disposed above 116 on the left side and 930 disposed on 118 on the right side of the write structure).
It would have been obvious to one of ordinary skill in the art to modify the embodiment of Komura with the electrodes of Sato in order to supply power to the write line and store data into the memory device from above.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek as applied to claim 12, and in further view of Dutta 1, and in further view of Dutta et al. (US 2023/0189660 A1; herein after Dutta 2).
PNG
media_image2.png
504
748
media_image2.png
Greyscale
Annotated Figure 22 – Dutta 2
Regarding claim 13, Reznicek teaches the manufacturing method of the semiconductor device according to claim 12, wherein
the substrate comprises a first region and a second region (Fig. 1-9: first region is comprised of all of memory device 100),
the magnetic tunnel junction structures and the write structure are disposed above the first region (Fig. 8: first region includes write structure 820 and MTJ pillar 510), and the manufacturing method further comprises:
forming an interconnection structure above the second region, wherein
the electrically conductive layer of the write structure and the interconnection structure are formed concurrently by the same process.
However, Dutta 1 discloses the claim limitations not disclosed in Reznicek:
a first region and second region (Fig. 1: memory region 100A and logic region 100B, logic and memory regions remain consistent throughout figures 1-6; [0022])
forming an interconnection structure above the second region (Fig. 6: Logic region contacts 157), wherein
the electrically conductive layer of the write structure (Fig. 6: upper contact 153; [0060]) and the interconnection structure are formed concurrently by the same process (Fig. 6; [0061], “Logic region contact(s) 157 may be formed simultaneously with upper contact 153”).
Dutta 1 also discloses in paragraphs 60 and 61, “suitable formation methods such as damascene, dual-damascene, deposition, plating, combinations thereof, or the like”, are suitable for forming both the upper contact 153 and the logic region contact(s) 157, meaning that they can both be formed by the same processes.
It would have been obvious for one of ordinary skill in the art to modify the method of manufacturing the semiconductor device of Reznicek with the method of Dutta 1, in order to form the interconnection structure concurrently with the electrically conductive layer of the write structure and using the same process in order to decrease costs and manufacturing time of the device. Any of the disclosed formation methods by Dutta 1 would be a valid process for forming the interconnection structure concurrently with the electrically conductive layer.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Dutta 1 as applied to claim 13, and in further view of Dutta et al. (US 2023/0189660 A1; herein after Dutta 2).
PNG
media_image2.png
504
748
media_image2.png
Greyscale
Annotated Figure 22 – Dutta 2
Regarding claim 14, Reznicek does not explicitly disclose teaches the manufacturing method of the semiconductor device according to claim 13, wherein
the dielectric layer is formed above the first region and the second region, and a method of forming the interconnection structure comprises:
forming a second trench in the dielectric layer located above the second region, wherein
the first trench and the second trench are formed concurrently by the same process;
forming a contact hole under the second trench, wherein
the contact hole is connected with the second trench, and the
spin-orbit torque patterns are formed in the first trench before the contact hole is formed;
forming an electrically conductive material above the substrate, wherein
the electrically conductive material is partly formed in the first trench, partly formed in the second trench and the contact hole, and partly formed outside the first trench, the second trench, and the contact hole; and
performing a planarization process for removing the electrically conductive material located outside the first trench, the second trench, and the contact hole.
However, Dutta 2 teaches the limitations not disclosed by Reznicek wherein:
the dielectric layer is formed above the first region and the second region (Fig. 22: dielectric fill layer 250; [0075]), and a method of forming the interconnection structure comprises:
forming a second trench in the dielectric layer located above the second region (see annotated Fig. 22: second trench in logic area, [0075], also described as “via in the logic area”), wherein
the first trench and the second trench are formed (annotated Fig. 22: first trench is in the memory area and second trench is in the logic area; [0075], vias, analogous to trenches, formed in the logic and memory area “may be formed by any suitable combination of processes that are known to a person of skill in the art”) concurrently by the same process;
forming a contact hole under the second trench (see annotated Fig. 22, contact hole formed below second trench), wherein
the contact hole is connected with the second trench (see annotated Fig. 22: contact hole directly connected to second trench), and the
spin-orbit torque patterns are formed in the first trench before the contact hole is formed (Fig. 21: top electrode 238 is formed before the contact hole is formed)
forming an electrically conductive material above the substrate (Fig. 21: bottom and top electrodes 218, 254, 256 are all above the substrate; [0044]]); wherein
the electrically conductive material is partly formed in the first trench, partly formed in the second trench and the contact hole, and partly formed outside the first trench, the second trench, and the contact hole (annotated Fig. 22: top electrodes 254 and 256 are in the trenches and contact hole, while the bottom electrode 218 is not in the trenches or contact hole); and
performing a planarization process for removing the electrically conductive material located outside the first trench, the second trench, and the contact hole (Fig. 16: bottom electrode 218 is planarized by CMP process; [0062]).
However, Dutta 1 teaches in a separate embodiment the following limitations not disclosed by Reznicek or Dutta 2 wherein:
the first trench and the second trench are formed concurrently by the same process ([0090] – [0061], formation methods damascene and dual-damascene process is suitable to form both logic region contact(s) 157 and upper contact 153, it is well known to a person of ordinary skill in the art that the damascene process forms interconnections by patterning trenches, and is stated that the logic region contact(s) 157 may be formed simultaneously with upper contact 153);
It would have been obvious for one of ordinary skill in the art to modify the method of manufacturing the semiconductor device of Reznicek with the method of Dutta 2 and the damascene process of Dutta 1, in order to form the efficiently simplify and reduce the time constraints.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek as applied to claim 12, and in further view of Lin.
Regarding claim 15, Reznicek does not explicitly teach the manufacturing method of the semiconductor device according to claim 12, wherein the dielectric layer comprises:
a first layer; and
a second layer disposed on the first layer, wherein
the write structure is partly disposed in the first layer and partly disposed in the second layer, and
a dielectric constant of the second layer is lower than a dielectric constant of the first layer.
However, Lin teaches wherein the dielectric layer (Fig. 8: dielectric layers 602 and 601) comprises:
a first layer (Fig. 8: cap dielectric layer 601); and
a second layer disposed on the first layer (Fig. 8: dielectric layer 602),
wherein the write structure (Fig. 8: conductive features 702; [0048] may be word lines or bit lines, or the like) is partly disposed in the first layer and partly disposed in the second layer (Fig. 8; [0048], conductive features 702 penetrate through the dielectric portions and both 601 and 602 surround 702 in the horizontal direction), and
a dielectric constant of the second layer is lower than a dielectric constant of the first layer ([0046] and [0047], dielectric layer 601 is formed of a standard dielectric silicon nitride, silicon oxynitride, or the like, and dielectric layer 602 may be formed of a low-k dielectric material).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Reznicek with the dielectric layers of Lin in order to utilize the properties of the layer of lower dielectric constant to reduce signal interference in the write structure, while maintaining the magnetic field of the MTJ structure in the layer with the higher dielectric constant.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek as applied to claim 12, in view of Dutta 2 and in further view of Dutta 1.
Regarding claim 16, Reznicek does not explicitly teach the manufacturing method of the semiconductor device according to claim 12, wherein
the first trench is elongated in the first horizontal direction,
the magnetic tunnel junction structures are arranged in the first horizontal direction, and the method of forming the write structure further comprises:
forming a barrier layer in the first trench, wherein the barrier layer is formed on a surface of the first trench and the spin-orbit torque patterns,
the electrically conductive layer is formed on the barrier layer, and
a part of the barrier layer is sandwiched between one of the spin-orbit torque patterns and the dielectric layer in a second horizontal direction orthogonal to the first horizontal direction.
However, Dutta 2 teaches the following limitations not disclosed in Reznicek wherein:
the first trench is elongated in the first horizontal direction (see annotated Fig. 22: first trench extends in the direction away from the logic area),
the magnetic tunnel junction structures are arranged in the first horizontal direction (Fig. 20: MTJ stacks 236 in a horizontal row)
forming a barrier layer in the first trench (Fig. 22: layer 252 formed in the first trench; [0047], bottom metal liner layer 112 is the same as 252), wherein the barrier layer is formed on a surface of the first trench (Fig. 22: barrier layer 252 formed on 250) and the spin-orbit torque patterns
However, Dutta 1 teaches the following limitations not disclosed in Reznicek or Dutta 2 wherein the method of forming the write structure further comprises:
wherein the barrier layer is formed on a surface of the spin-orbit torque patterns (Fig. 6: barrier layer 115 is on lower contact 143),
the electrically conductive layer is formed on the barrier layer (Fig. 6: upper contact 153 is formed on 115), and
a part of the barrier layer is sandwiched between one of the spin-orbit torque patterns and the dielectric layer in a second horizontal direction orthogonal to the first horizontal direction (Fig. 6: the barrier layer is on the side of the lower contact 143 which is between the dielectric layer 141).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Reznicek with the barrier layer of Dutta 2 in order to prevent diffusion between the dielectric layers and the write structure.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Reznicek in view of Dutta 2 with the barrier layer of Dutta 1 in order to prevent diffusion between the layers of the write structure.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek as applied to claim 12, and in further view of Komura.
Regarding claim 17, Reznicek does not explicitly teach the manufacturing method of the semiconductor device according to claim 11, wherein each of the magnetic tunnel junction structures comprises:
a free layer; and
a spin-orbit torque layer disposed above the free layer, wherein
each of the spin-orbit torque patterns is connected with the spin-orbit torque layer of the magnetic tunnel junction structure disposed under spin-orbit torque pattern.
However, Komura teaches wherein each of the magnetic tunnel junction structures comprises:
a free layer (Fig. 1 and 5: ferromagnetic metal layer 23; [0057]); and
a spin-orbit torque layer (Fig. 1 and 5: cap layer 24; [0069] – [0072], stated to require spin conductivity for spin transfer from the spin-orbit torque wiring) disposed above the free layer (Fig. 5: 24 above 23), wherein
each of the spin-orbit torque patterns is connected with the spin-orbit torque layer of the magnetic tunnel junction structure disposed under the spin-orbit torque pattern (Fig. 5: 41 and 24 connected through junction 24’; [0118]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Reznicek with the embodiment of Komura in order to have the write structure disposed above the MTJ structure for ease of sending signals to the write structure, and to have separate SOT patterns and layers. The SOT patterns are for generating the spin orbit torque, and the SOT layer for its spin conductivity to transfer the torque through to the free layer.
Claims 18 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Komura and in further view of Lee.
Regarding claim 18, Reznicek and Komura do not explicitly teach the semiconductor device according to claim 17, wherein a material composition of the spin-orbit torque patterns is different from a material composition of the spin-orbit torque layers.
However, Lee teaches a material composition of the spin-orbit torque patterns (Fig. 2a: conductive patterns 130; [0055] – [0057]) is different from a material composition of the spin-orbit torque layers (Fig. 2a: conductive patterns 130; [0058], “conductive patterns 130 may include a material different from conductive patterns 150”).
It would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention to use the materials of Lee in the embodiment of Reznicek in view of Komura in order to have different materialistic properties, such as resistivity, required by each of the SOT patterns and SOT layers.
Regarding claim 19, Reznicek and Komura do not explicitly teach, the semiconductor device according to claim 17, wherein a hardness of each of the spin-orbit torque patterns is lower than a hardness of each of the spin-orbit torque layers.
However, applicant discloses in paragraph [0023], hafnium (Hf), rhenium (Re), ruthenium (Ru) may be used for the SOT layers has increased hardness from tungsten (W), gold (Au), and tantalum (Ta) which may be used for the SOT patterns. However, Lee discloses the same materials disclosed as applicant in an SOT pattern and SOT layers ([0054] – [0058], conductive line SOL includes conductive patterns 130 and 150 stated to be made from a list of materials which discloses hafnium (Hf), rhenium (Re), ruthenium (Ru), tungsten (W), gold (Au), and tantalum (Ta) etc.). Because these materials disclose by Lee are the same as the materials disclosed by applicant, it would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention that these same materials would exhibit the same claimed properties (ie. a hardness of the spin torque layer being greater than the hardness of the spin torque pattern).
Regarding claim 20, Reznicek and Komura do not explicitly teach, the semiconductor device according to claim 17, wherein electrical resistivity of each of the spin-orbit torque patterns is lower than electrical resistivity of each of the spin-orbit torque layers.
However, applicant discloses in paragraph [0023], tungsten (W), gold (Au), and tantalum (Ta) which may be used for the SOT patterns has lower resistivity from hafnium (Hf), rhenium (Re), ruthenium (Ru) may be used for the SOT layers. However, Lee discloses the same materials disclosed as applicant in an SOT pattern and SOT layers ([0054] – [0058], conductive line SOL includes conductive patterns 130 and 150 stated to be made from a list of materials which discloses hafnium (Hf), rhenium (Re), ruthenium (Ru), tungsten (W), gold (Au), and tantalum (Ta) etc.). . Because these materials disclose by Lee are the same as the materials disclosed by applicant, it would have been obvious of one of ordinary skill in the art before the effective filing date of the claimed invention that these same materials would exhibit the same claimed properties (ie. a resistivity of the spin torque pattern being lower than the resistivity of the spin torque layer) .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN HOANG TRAN whose telephone number is (571)270-0290. The examiner can normally be reached 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN HOANG TRAN/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights