CTNF 18/413,073 CTNF 101989 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Applicants’ election of invention I drawn to claims 1-3, 5, and 8-9 and appended claims 21-34 are acknowledge. Claims 4, 6-7, and 10-20, drawn to an unelected invention, are cancelled. Claims 1-3, 5, 8-9, and 21-34 are examined herein. Election/Restrictions 08-06 AIA Claim s 4, 6-7, and 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/12/2026 . 08-25-01 AIA Applicant’s election without traverse of claims 1-3, 5, 8-9, and 21-34 in the reply filed on 05/12/2026 is acknowledged. 08-23-02 AIA Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i). Claim Objections 07-29-01 AIA Claim 30 is objected to because of the following informalities: In line 3, “an housing” should read “a housing” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 24-29 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 24 recites the limitation “the MEMS chip” in line 6. The claim make reference to a chip not a MEMS chip. There is insufficient antecedent basis for this limitation in the claim. Similarly, claims 25-29 are further rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph based on their dependency to claim 24. 07-34-05 AIA Claim 32 recites the limitation “ the electromagnetic shielding housing ” in line 2 . There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1-3, 5, 8-9, 21-29, 31, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US Patent 8,853,839) in view of Lin (US Patent Application Publication 2023/0395461A1) and Kautzsch (US Patent Application Publication 2018/0297838A1) . Regarding claim 1, Gao (US Patent 8,853,839) teaches a semiconductor package structure (conventional device package 1, Figure 1, col 3, line 19), comprising: a substrate (package substrate 5, Figure 1, col 3, line 28-29); and a chip (integrated device 3, Figure 1, col3, lines 24-26) disposed on the substrate, as claimed. Gao (US Patent 8,853,839) is silent to teach a molding material disposed on the substrate and surrounding the chip, wherein the chip includes: a cavity; and a movable element disposed within and movable within the cavity and configured to sense or output a force. In an analogous art, Lin (US Patent Application Publication 2023/0395461A1) teaches a molding material (package component encapsulant 301, Figure 3, paragraph 0020, lines 1-2, teaches a package component encapsulant is formed on and around the integrated circuit dies) disposed on the substrate (package component substrate 101, Figure 3) and surrounding the chip (first integrated circuit dies 209, Figure 3), as claimed. PNG media_image1.png 305 526 media_image1.png Greyscale Additionally, Kautzsch (US Patent Application Publication 2018/0297838A1) teaches wherein the chip includes: a cavity (trench 14, Figure 4, paragraph 0029, line 4); and a movable element (movably suspended mass 8, Figure 4, paragraph 0028, line 4) disposed within and movable within the cavity and configured to sense or output a force, as claimed. Therefore, it would have been obvious for someone of ordinary sill in the art before the effective filing date of the claimed invention to have modified the teachings of Gao (US Patent 8,853,839) by replacing the chip with the structure of Lin (US Patent Application Publication 2023/0395461A1) thereby reducing the force experienced by the chip. Furthermore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings Gao (US Patent 8,853,839) with the teachings of Kautzsch (US Patent Application Publication 2018/0297838A1) thereby having a chip configured to sense or output a force. Regarding claim 2, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) further teaches wherein the chip is a MEMS device (Figure 1, col 3, lines 26-27, teaches the integrated device may be, for example, an integrated circuit die or a MEMS die), as claimed. Regarding claim 3, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Lin (US Patent Application Publication US2023/0395461A1) further teaches wherein a top surface of the molding material is substantially coplanar with a top surface of the chip exposed through the molding material (Figure 3, paragraph 0020, lines 18-21, teaches the top surfaces of the integrated circuit dies and the package component encapsulant are coplanar (within process variations) such that they are level with one another), as claimed. PNG media_image2.png 305 628 media_image2.png Greyscale Regarding claim 5, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) further teaches further comprising a housing (package lid 7, Figure 1, col 3, lines 28-29, teaches a package lid is arranged over the integrated device and connects to the package substrate) disposed on the substrate, covering the chip and the molding material, as claimed. Regarding claim 8, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) further teaches wherein an exterior surface of the housing is coupled to and coplanar with a sidewall of the substrate (Figure 1, claim 22, col 16, lines 30-33, teaches the package substrate includes a base and a wall extending from the base, and wherein the lid is substantially planar), as claimed. PNG media_image3.png 217 423 media_image3.png Greyscale Regarding claim 9, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) further teaches wherein the housing is made of a metallic material (col 3, lines 32-33, teaches package lid may be conductive (e.g., metal or coated with metal), as claimed. Regarding claim 21, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) further teaches wherein an interior surface of a top of the housing faces a top surface of the chip (Figure 1), as claimed. PNG media_image4.png 217 423 media_image4.png Greyscale Regarding claim 22, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Gao (US Patent 8,853,839) further teaches wherein the interior surface of the housing is spaced apart from the top surface of the chip by a gap (cavity 11, Figure 1, col 3, lines 31-32, teaches the area between the package substrate and the package lid defines a cavity), as claimed. Regarding claim 23, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 1, as claimed. Since the chip of Gao (US Patent 8,853,839) was replaced with the structure of Lin (US Patent Application Publication US2023/0395461A1) to include the molding material around the chip. Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) further teach wherein the molding material is partially disposed in a space defined by the substrate, the chip, and the housing, as claimed. Regarding claim 24, Gao (US Patent 8,853,839) teaches a semiconductor package structure (conventional device package 1, Figure 1, col 3, line 19), comprising: a substrate (package substrate 5, Figure 1, col 3 line 28-29); a chip disposed on the substrate and electrically connected to electrical circuitry of the substrate (integrated device 3, Figure 1, col3, lines 24-26, teaches the integrated device is physically and electrically coupled with a package substrate), a metallic housing disposed on the substrate and covering the MEMS chip (package lid 7, Figure 1, col 3, lines 32-33, teaches package lid may be conductive (e.g., metal or coated with metal)), wherein an exterior surface of the metallic housing is coupled to and continuous with an edge of the substrate (package lid 7, Figure 1, claim 22, col 16, lines 30-33, teaches the package substrate includes a base and a wall extending from the base, and wherein the lid is substantially planar); and a gap (cavity 11, Figure 1, col 3, lines 31-32, teaches the area between the package substrate and the package lid defines a cavity) is formed between the top surface of the chip and an interior surface of the metallic housing, as claimed. PNG media_image3.png 217 423 media_image3.png Greyscale Gao (US Patent 8,853,839) is silent to teach the chip including one or more movable elements disposed within a cavity; and a molding structure surrounding lateral sides of the chip to expose a top surface of the chip from the molding structure. In an analogous art, Kautzsch (US Patent Application Publication 2018/0297838A1) teaches the chip including one or more movable elements disposed within a cavity (movably suspended mass 8 + trench 14, Figure 4, paragraph 0029, lines 1-8, teaches the cavity is formed in the bulk semiconductor substrate, e.g. using a silicon on nothing process. The movably suspended mass is defined in the bulk semiconductor substrate by one or more trenches extending from a main surface area of the bulk semiconductor substrate to the cavity. Hence, the cavity may be formed beneath a main surface area of the semiconductor substrate in a region of the future movably suspended mass), as claimed. Additionally, Lin (US Patent Application Publication 2023/0395461A1) teaches a molding structure surrounding lateral sides of the chip to expose a top surface of the chip from the molding structure (package component encapsulation 301, Figure 3, paragraph 0020, lines 18-21, teaches the top surfaces of the integrated circuit dies and the package component encapsulant are coplanar (within process variations) such that they are level with one another), as claimed. PNG media_image5.png 305 526 media_image5.png Greyscale Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Gao (US Patent 8,853,839) with the teachings of Kautzsch (US Patent Application Publication 2018/0297838A1) thereby having a chip configured to sense or output a force. Furthermore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings Gao (US Patent 8,853,839) by replacing the chip with the structure of Lin (US Patent Application Publication 2023/0395461A1) thereby reducing the force experienced by the chip while leaving a top surface exposed so as to not restrict the operation of the MEMs chip. Regarding claim 25, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 24, as claimed. Kautzsch (US Patent Application Publication US2018/0297838A1) further teaches wherein the chip comprises: a device substrate (bulk semiconductor substrate 4, Figure 4, paragraph 0028, lines 3-4, teaches the MEMS device comprises a bulk semiconductor substrate); a support member disposed on the device substrate (bulk semiconductor substrate 4, Figure 4); and a capping member disposed on the support member (cap structure 10, Figure 4, paragraph 0028, line 3-5, teaches the MEMS device comprises a bulk semiconductor substrate a cavity a movably suspended mass, a cap structure), so that the capping member and the device substrate are bonded by the support member (paragraph 0048, lines 3-5, teaches the cap structure is arranged above the semiconductor substrate and attached thereto). PNG media_image6.png 407 475 media_image6.png Greyscale Regarding claim 26, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 25, as claimed. Kautzsch (US Patent Application Publication US2018/0297838A1) further teaches wherein the one or more movable elements are disposed between the device substrate and the capping member (Figure 4, paragraph 0031, teaches the cap structure (or bearing structure, support structure) is arranged on the main surface area of the bulk semiconductor substrate. In other words, the cap structure may be arranged on a remaining portion of the semiconductor substrate. The cap structure may not (mechanically) contact the movably suspended mass. In other words, the cap structure is spaced apart from the movably suspended mass). Regarding claim 27, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 24, as claimed. Lin (US Patent Application Publication US2023/0395461A1) further teaches wherein a top surface of the molding structure is substantially coplanar with the top surface of the chip (Figure 3, paragraph 0020, lines 18-21, teaches the top surfaces of the integrated circuit dies and the package component encapsulant are coplanar (within process variations) such that they are level with one another). PNG media_image5.png 305 526 media_image5.png Greyscale Regarding claim 28, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 24, as claimed. Lin (US Patent Application Publication US2023/0395461A1) further teaches wherein a height of the molding structure is substantially equal to a height of the chip (Figure 3). PNG media_image5.png 305 526 media_image5.png Greyscale Regarding claim 29, Gao (US Patent 8,853,839), Lin (US Patent Application Publication US2023/0395461A1), and Kautzsch (US Patent Application Publication US2018/0297838A1) teach the semiconductor package of claim 24, as claimed. Since the chip of Gao (US Patent 8,853,839) was replaced with the structure of Lin (US Patent Application Publication US2023/0395461A1) to include the molding material around the chip; the chip and molding material will have a height larger than the space remaining in the cavity of Gao (US Patent 8,853,839). Therefore, Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) further teach wherein a height of the molding structure is greater than a height of the gap, as claimed. Regarding claim 31, Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) teach the semiconductor package of claim 30, as claimed. Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) are silent to teach wherein the chip includes: a cavity; and a movable element disposed movably within the cavity. In an analogous art, Kautzsch (US Patent Application Publication US2018/0297838A1) teaches wherein the chip includes: a cavity (trench 14, Figure 4, paragraph 0029, line 4, teaches); and a movable element (movably suspended mass 8, Figure 4, paragraph 0028, line 4) disposed movably within the cavity. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) with the teachings of Kautzsch (US Patent Application Publication 2018/0297838A1) thereby having a chip configured to sense or output a force. Regarding claim 33, Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) teach the semiconductor package of claim 30, as claimed. Kautzsch (US Patent Application Publication US2018/0297838A1) further teaches wherein the chip comprises: a device substrate (bulk semiconductor substrate 4, Figure 4, paragraph 0028, lines 3-4, teaches the MEMS device comprises a bulk semiconductor substrate a cavity a movably suspended mass, a cap structure); a support member disposed on the device substrate (bulk semiconductor substrate 4, Figure 4); and a capping member (cap structure 10, Figure 4, paragraph 0028, line 3-5, teaches the MEMS device comprises a bulk semiconductor substrate a cavity a movably suspended mass, a cap structure) disposed on the support member, so that the capping member and the device substrate are bonded by the support member (paragraph 0048, lines 3-5, teaches the cap structure is arranged above the semiconductor substrate and attached thereto) . PNG media_image6.png 407 475 media_image6.png Greyscale 07-21-aia AIA Claim (s) 30, 32, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US Patent 8,853,839) in view of Lin (US Patent Application Publication 2023/0395461A1) . Regarding claim 30, Gao (US Patent 8,853,839) teaches a semiconductor package structure (conventional device package 1, Figure 1, col 3, line 19), comprising: a chip on a substrate (integrated device 3 + package substrate 5, Figure 1, col 3, lines 24-26, teaches the integrated device is physically and electrically coupled with a package substrate); and a housing (package lid 7, Figure 1, col 3, lines 28-29, teaches a package lid is arranged over the integrated device and connects to the package substrate) disposed on the substrate and enclosing the chip, as claimed. Gao (US Patent 8,853,839) is silent to teach a molding structure disposed on the substrate and between the chip and the housing, wherein a top surface of the molding structure is substantially coplanar with a top surface of the chip. In an analogous art, Lin (US Patent Application Publication US2023/0395461A1) teaches a molding structure disposed on the substrate and between the chip and the housing (package component encapsulant 301, Figure 3, paragraph 0020, lines 1-4, teaches a package component encapsulant is formed on and around the integrated circuit dies), wherein a top surface of the molding structure is substantially coplanar with a top surface of the chip (Figure 5, paragraph 0020, lines 18-21, teaches the top surfaces of the integrated circuit dies and the package component encapsulant are coplanar (within process variations) such that they are level with one another), as claimed. PNG media_image5.png 305 526 media_image5.png Greyscale Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Gao (US Patent 8,853,839) by replacing the chip with the structure of Lin (US Patent Application Publication 2023/0395461A1) thereby reducing the force experienced by the chip. Regarding claim 32, Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) teach the semiconductor package of claim 30, as claimed. Gao (US Patent 8,853,839) further teaches wherein the electromagnetic shielding housing is made of a metallic material (package lid 7, Figure 1, col 3, lines 32-33, teaches the package lid may be conductive (e.g., metal or coated with metal)), and an exterior surface of the electromagnetic shielding housing is substantially coplanar with an edge of the substrate (Figure 1, claim 22, col 16, lines 30-33, teaches the package substrate includes a base and a wall extending from the base, and wherein the lid is substantially planar). PNG media_image3.png 217 423 media_image3.png Greyscale Regarding claim 34, Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) teach the semiconductor package of claim 30, as claimed. Gao (US Patent 8,853,839) and Lin (US Patent Application Publication US2023/0395461A1) further teach wherein a gap (cavity 11, Figure 1, col 3, lines 31-32, teaches the area between the package substrate and the package lid defines a cavity) is present over the chip and the molding material within the housing. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.M.A./Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/413,073 Page 2 Art Unit: 2898 Application/Control Number: 18/413,073 Page 3 Art Unit: 2898 Application/Control Number: 18/413,073 Page 4 Art Unit: 2898 Application/Control Number: 18/413,073 Page 5 Art Unit: 2898 Application/Control Number: 18/413,073 Page 6 Art Unit: 2898 Application/Control Number: 18/413,073 Page 7 Art Unit: 2898 Application/Control Number: 18/413,073 Page 8 Art Unit: 2898 Application/Control Number: 18/413,073 Page 9 Art Unit: 2898 Application/Control Number: 18/413,073 Page 10 Art Unit: 2898 Application/Control Number: 18/413,073 Page 11 Art Unit: 2898 Application/Control Number: 18/413,073 Page 12 Art Unit: 2898 Application/Control Number: 18/413,073 Page 13 Art Unit: 2898
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