DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 4, 8, 10, 13, and 19 are amended. Claims 1-20 are present for examination.
Response to Arguments
Applicant’s arguments, see page 1, filed July 15, 2026, with respect to title objection have been fully considered and are persuasive. The title objection of April 17, 2026 has been withdrawn.
Applicant’s arguments, see page 1, filed July 15, 2026, with respect to the claim objections have been fully considered and are persuasive. The claim objections of April 17, 2026 has been withdrawn.
Applicant’s arguments, see pages 1-4, filed July 15, 2026, with respect to the rejection(s) of claim(s) 1-2, 5-8, 11-17, and 20 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kao (US 2021/0320052 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the geometry and relative positioning of the second through-substrate via with respect to the first through-substrate via, as well as the relative widths of the surfaces of the second through-substrate via with respect to the first through-substrate via (e.g. wherein the second through-substrate via is horizontally adjacent to the first through-substrate via; the second through-substrate via has a third surface facing the first interconnect structure and a fourth surface facing the pad; a width of the fourth surface is greater than a width of the third surface; wherein the width of the second surface is approximately equal to the width of the fourth surface; and the width of the first surface is approximately equal to the width of the third surface). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0359449 A1) in view of Kao (US 2021/0320052 A1).
Claim 1, Chen discloses a semiconductor package structure (semiconductor structure P1, circuit element 300, and substrate 500 form a semiconductor package structure, hereinafter, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46) comprising:
a first semiconductor component (integrated circuit component 130A is a first semiconductor component, hereinafter, first semiconductor component 130A, [0071], Figs. 14 and 46) having a first substrate (semiconductor substrate 131 is a first substrate, hereinafter, first substrate 131, [0057], Figs. 14 and 46) and a first interconnect structure (interconnect structure 132 is a first interconnect structure, hereinafter, first interconnect structure 132, [0057], Figs. 14 and 46), wherein the first interconnect structure 132 is disposed on a first side (active surface 131a is a first side, hereinafter, first side 131a, [0023], Figs. 8, 14, and 46) of the first substrate 131 (first interconnect structure 132 is disposed on a first side 131a of the first substrate 131, [0023], Figs. 8, 14, and 46);
a second semiconductor component (substrate 500 is a second semiconductor component and includes metallization layers 530, hereinafter, second semiconductor component 500/530, [0119], Figs. 14 and 46) having a second substrate (second semiconductor component 500 includes a second substrate 500, [0119], Figs. 14 and 46) and a second interconnect structure (second semiconductor component 500/530 includes conductive terminals 400, contact pads 510, metallization layers 530 form a second interconnect structure 400/510/530, hereinafter, second interconnect structure 400/510/530, [0119], Figs. 14 and 46);
a bonded structure (redistribution circuit structure 160 and circuit element 300 form a bonded structure, hereinafter, bonded structure 160/300, [0123], Figs. 14 and 46) between and bonded to the first interconnect structure 132 and the second interconnect structure 530 (bonded structure 160/300 is between and bonded to the first interconnect structure 132 and the second interconnect structure 400/510/530, [0123], Figs. 14 and 46);
a first through-substrate via (conductive vias 136 are through semiconductor vias and the through semiconductor via on the left-hand side (i.e. (-) X-direction) is the first through-substrate via, hereinafter, first through-substrate via 136L, [0040], Figs. 14 and 46) penetrating the first substrate 131 from a second side (bottom surface 131b” of the semiconductor substrate 131 is the second side, hereinafter, second side 131b”, [0040], Figs. 14 and 46) to the first side 131a (first through-substrate via 136L penetrates the first substrate 131 from a second side 131b” to the first side 131a, [0040], Figs. 14 and 46), wherein the second side 131b” is opposite to the first side 131a (second side 131b” is opposite to the first side 131a, [0040], Figs. 14 and 46);
a pad (connecting pads 230 is a pad, hereinafter, pad 230, [0057], Figs. 14 and 46) disposed over the second side 131b” of the first substrate 131 (pad 230 is disposed over the second side 131b” of the first substrate 131, [0057], Figs. 14 and 46); and
a conductive feature (connecting vias 240 is a conductive feature, hereinafter, conductive feature 240, [0057], Figs. 14 and 46) disposed over the second side 131b” of the first substrate 131 (conductive feature 240 is disposed over the second side 131b” of the first substrate 131, [0057], Figs. 14 and 46) and between the first through-substrate via 136L and the pad 230 (conductive feature 240 is disposed between the first through-substrate via 136L and the pad 230, [0057], Figs. 14 and 46),
wherein the conductive feature 240 electrically connects the first through-substrate via 136L to the pad 230 (conductive feature 240 electrically connects the first through-substrate via 136L to the pad 230, [0057], Figs. 14 and 46), and the conductive feature 240 is electrically connected to the first interconnect structure 132 by the first through-substrate via 136L (conductive feature 240 is electrically connected to the first interconnect structure 132 by the first through-substrate via 136L, [0057], Figs. 14 and 46).
Chen does not explicitly disclose wherein the first through-substrate via has a first surface facing the first interconnect structure and a second surface facing the pad, and a width of the second surface is greater than a width of the first surface,
However, Kao discloses wherein the first through-substrate via has a first surface facing the first interconnect structure and a second surface facing the pad (Kao, TSV 104 is a first through-substrate via, hereinafter, first through-substrate via 104 has a first surface facing the first interconnect structure 116, hereinafter, first surface 116/104 and a second surface facing the pad 112c hereinafter, second surface 112c/104, [0059], Fig. 8A; Chen, first through-substrate via 136L, pad 230, and first interconnect structure 132, [0040], Figs. 14 and 46), and a width of the second surface is greater than a width of the first surface (Kao, width of the second surface 112c/104 is greater than a width of the first surface 116/104 , [0059], Fig. 8A; Chen, first through-substrate via 136L, pad 230, and first interconnect structure 132, [0040], Figs. 14 and 46), The combination to utilize a through-substrate via having one surface wider than the other surface ensures for proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a through-substrate via having one surface wider than the other surface to ensure proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
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Annotated Fig. 14 (Chen) – Illustrates semiconductor structure P1 which further including a first semiconductor component 130A having a first substrate 131 and a first interconnect structure 132, wherein the first interconnect structure 132 is disposed on a first side 131a of the first substrate 131. It is noted that the semiconductor structure P1 is then inverted (i.e. (+) Z-direction inverts to (-) Z-direction) and mounted to form the resultant semiconductor structure (Fig. 46).
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Fig. 46 (Chen) – Illustrates a semiconductor package structure P1/300/500 further including a first semiconductor component 130A having a first substrate 131 and a first interconnect structure 132, a second semiconductor component 500/530 having a second substrate 500 and a second interconnect structure 400/510/530; further comprising a pad 230 disposed over the second side 131b” of the first substrate 131; and a conductive feature 240 disposed over the second side 131b” of the first substrate 131 and between the first through-substrate via 136L and the pad 230.
Claim 2, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 1.
Chen/Kao discloses wherein the bonded structure 160/300 comprises:
a first dielectric layer (Chen, one or more dielectric layers 332 is a first dielectric layer, hereinafter, first dielectric layer 332, [0126], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A);
a first metallization feature (Chen, metallization layer 334 is a first metallization feature, hereinafter, first metallization feature 334, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) disposed in the first dielectric layer 332 (Chen, first metallization feature 334 is disposed in the first dielectric layer 332, [0130], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) and electrically connected to the first interconnect structure 132 (Chen, first metallization feature 334 is electrically connected to the first interconnect structure 132, [0130] – [0134], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A);
a second dielectric layer (Chen, one or more dielectric layers 342 is a second dielectric layer, hereinafter, second dielectric layer 342, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
a second metallization feature (Chen, metallization layer 344 is a second metallization feature, hereinafter, second metallization feature 344, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) disposed in the second dielectric layer 342 (Chen, second metallization feature 344 is disposed in the second dielectric layer 342, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) and electrically connected to the second interconnect structure 400/510/530 (Chen, second metallization feature 344 is electrically connected to the second interconnect structure 400/510/530, [0125] – [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A),
wherein the first dielectric layer 332 is bonded to the second dielectric layer 342 (Chen, first dielectric layer 332 is bonded to the second dielectric layer 342, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), and the first metallization feature 334 is bonded to the second metallization feature 344 (Chen, first metallization feature 334 is bonded to the second metallization feature 344, [0127], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 3, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 1.
Chen/Kao discloses wherein each of the first interconnect structure 132 and the second interconnect structure 400/510/530 comprises an uppermost metallization layer (Chen, first interconnect structure 132 includes protection layer 135, connecting pads 133, and plurality of connecting vias 134 which form an uppermost metallization layer, hereinafter, uppermost metallization layer of the first interconnect structure 133/134/135, [0021], Figs. 14 and 46; second interconnect structure 400/510/530 includes a solder mask layer 352b and a plurality of bonding pads 354b which form an uppermost metallization layer, hereinafter, uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Chen does not explicitly disclose a thickness of the conductive feature 240 is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135, and greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b.
However, Chen discloses a thickness of the conductive feature (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), and greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, thickness of the uppermost metallization layer of the first interconnect structure, and thickness of the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed metallization layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
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Annotated Fig. 46 (Chen) – Illustrates a semiconductor package structure P1/300/500 wherein the thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 as greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b.
Claim 4, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 3.
Chen does not explicitly disclose wherein the thickness of the conductive feature is greater a sum of the thickness of the uppermost metallization layer of the first interconnect structure and the thickness of the uppermost metallization layer of the second interconnect structure.
However, Chen/Kao discloses wherein the thickness of the conductive feature 240 (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the thickness of the uppermost metallization layer of the second interconnect structure 352b/354b (Chen, thickness of conductive feature 240 is greater than a thickness of a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, sum of the thickness of the uppermost metallization layer of the first interconnect structure and the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed metallization layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 5, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 1.
Chen/Kao discloses wherein the first interconnect structure 132 comprises a lowermost metallization layer (Chen, first interconnect structure 132 includes protection layer 250, conductive feature 240, and pad 230 which forms a lowermost metallization layer, hereinafter, lowermost metallization layer of the first interconnect structure 230/240/250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) coupled to the first through-substrate via 136L (Chen, lowermost metallization layer of the first interconnect structure 230/240/250 is coupled to the first through-substrate via 136L, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 6, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 1.
Chen/Kao discloses further comprising a second through-substrate via (Chen, conductive vias 136 are through semiconductor vias and the through semiconductor via on the right-hand side (i.e. (+) X-direction) is the second through-substrate via, hereinafter, second through-substrate via 136R, [0040], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) penetrating the first substrate 131 from the second side 131b” to the first side 131a (Chen, second through-substrate via 136R penetrates the first substrate 131 from a second side 131b” to the first side 131a, [0040], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), wherein the second through-substrate via 136R is in contact with a dielectric layer of the first interconnect structure 132 (Chen, second through-substrate via 136R is in contact with dielectric layer 132a, which is a dielectric layer 132a of the first interconnect structure 132, hereinafter, dielectric layer of the first interconnect structure 132a, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 7, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 1.
Chen/Kao discloses further comprising a redistribution layer (RDL) (Chen, interconnect structure 220 is a redistribution layer (RDL), hereinafter, RDL 220, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) disposed on the second side 131b” of the first substrate 131 (Chen, RDL 220 is disposed on the second side 131b” of the first substrate 131, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), wherein the RDL 220 comprises:
at least a metallization layer (Chen, metallization layer 224 is as least a metallization layer, hereinafter, metallization layer of the RDL 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
a top dielectric layer (Chen, protection layer 250 is a top dielectric layer, hereinafter, top dielectric layer 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the metallization layer 224 (Chen, top dielectric layer 250 is over the metallization layer 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), wherein the conductive feature 240 is disposed in the top dielectric layer 250 and electrically connected to the metallization layer 224 (Chen, conductive feature 240 is disposed in the top dielectric layer 250 and electrically connected to the metallization layer 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 8, Chen discloses a semiconductor package structure (semiconductor structure P1, circuit element 300, and substrate 500 form a semiconductor package structure, hereinafter, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46) comprising: a first semiconductor component (integrated circuit component 130A is a first semiconductor component, hereinafter, first semiconductor component 130A, [0071], Figs. 14 and 46) having a first substrate (semiconductor substrate 131 is a first substrate, hereinafter, first substrate 131, [0057], Figs. 14 and 46) and a first interconnect structure (interconnect structure 132 is a first interconnect structure, hereinafter, first interconnect structure 132, [0057], Figs. 14 and 46);
a second semiconductor component (core portion 310 and vias 320 are a second semiconductor component, hereinafter, second semiconductor component 310/320, [0123], Figs. 14 and 46) having a second substrate (second semiconductor component 310/320 includes a substrate, hereinafter, second substrate 310, [0123], Figs. 14 and 46) and a second interconnect structure (second semiconductor component 310/320 includes a second interconnect structure, hereinafter, second interconnect structure 320, [0123], Figs. 14 and 46);
a third semiconductor component (substrate 500 is a third semiconductor component and includes metallization layers 530, hereinafter, third semiconductor component 500/530, [0119], Figs. 14 and 46) having a third substrate (third semiconductor component 500 includes a third substrate 500, [0119], Figs. 14 and 46) and a third interconnect structure (third semiconductor component 500/530 includes conductive terminals 400, contact pads 510, metallization layers 530 form a third interconnect structure 400/510/530, hereinafter, third interconnect structure 400/510/530, [0119], Figs. 14 and 46);
a first bonded structure (redistribution circuit structure 160 is a first bonded structure, hereinafter, first bonded structure 160, [0123], Figs. 14 and 46) between the first interconnect structure 132 and the second interconnect structure 320 (first bonded structure 160 is between the first interconnect structure 132 and the second interconnect structure 320, [0123], Figs. 14 and 46);
a second bonded structure (redistribution circuit structure 340 is a second bonded structure, hereinafter, second bonded structure 340, [0123], Figs. 14 and 46) between the second substrate 310 and the third interconnect structure 400/510/530 (second bonded structure 340 is between the second substrate 310 and the third interconnect structure 400/510/530, [0123], Figs. 14 and 46);
a first through-substrate via (conductive vias 136 are through semiconductor vias and the through semiconductor via on the left-hand side (i.e. (-) X-direction) is the first through-substrate via, hereinafter, first through-substrate via 136L, [0040], Figs. 14 and 46) penetrating the first substrate 131 (first through-substrate via 136L penetrates the first substrate 131, [0040], Figs. 14 and 46) and electrically connected to the first interconnect structure 132 (first through-substrate via 136L is electrically connected to the first interconnect structure 132, [0057], Figs. 14 and 46);
a pad (connecting pads 230 is a pad, hereinafter, pad 230, [0057], Figs. 14 and 46) disposed over the first substrate 131 (pad 230 is disposed over the first substrate 131, [0057], Figs. 14 and 46) on a side opposite to the first interconnect structure 132 (bottom surface 131b” of the semiconductor substrate 131 is a side opposite to the first interconnect structure 132, hereinafter, side opposite to the first interconnect structure 131b”, [0040], Figs. 14 and 46); and
a conductive feature (connecting vias 240 is a conductive feature, hereinafter, conductive feature 240, [0057], Figs. 14 and 46) disposed between the first through-substrate via 136L and the pad 230 (conductive feature 240 is disposed between the first through-substrate via 136L and the pad 230, [0057], Figs. 14 and 46),
wherein the conductive feature 240 electrically connects the first through-substrate via 136L to the pad 230 (conductive feature 240 electrically connects the first through-substrate via 136L to the pad 230, [0057], Figs. 14 and 46), and the conductive feature 240 is electrically connected to the first interconnect structure 132 by the first through-substrate via 136L (conductive feature 240 is electrically connected to the first interconnect structure 132 by the first through-substrate via 136L, [0057], Figs. 14 and 46).
Chen does not explicitly disclose wherein the first through-substrate via has a first surface facing the first interconnect structure and a second surface facing the pad, and a width of the second surface is greater than a width of the first surface,
However, Kao discloses wherein the first through-substrate via has a first surface facing the first interconnect structure and a second surface facing the pad (Kao, TSV 104 is a first through-substrate via, hereinafter, first through-substrate via 104 has a first surface facing the first interconnect structure 116, hereinafter, first surface 116/104 and a second surface facing the pad 112c hereinafter, second surface 112c/104, [0059], Fig. 8A; Chen, first through-substrate via 136L, pad 230, and first interconnect structure 132, [0040], Figs. 14 and 46), and a width of the second surface is greater than a width of the first surface (Kao, width of the second surface 112c/104 is greater than a width of the first surface 116/104 , [0059], Fig. 8A; Chen, first through-substrate via 136L, pad 230, and first interconnect structure 132, [0040], Figs. 14 and 46), The combination to utilize a through-substrate via having one surface wider than the other surface ensures for proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a through-substrate via having one surface wider than the other surface to ensure proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
Claim 9, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 8.
Chen/Kao discloses wherein each of the first interconnect structure 132 and the second interconnect structure 320 comprises an uppermost metallization layer (Chen, first interconnect structure 132 includes protection layer 135, connecting pads 133, and plurality of connecting vias 134 which form an uppermost metallization layer, hereinafter, uppermost metallization layer of the first interconnect structure 133/134/135, [0021], Figs. 14 and 46; second interconnect structure 320 forms an uppermost metallization layer, hereinafter, uppermost metallization layer of the second interconnect structure 320, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Chen does not explicitly disclose a thickness of the conductive feature is greater than a thickness of the uppermost metallization layer of the first interconnect structure, and greater than a thickness of the uppermost metallization layer of the second interconnect structure.
However, Chen discloses a thickness of the conductive feature (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), and greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, thickness of the uppermost metallization layer of the first interconnect structure, and thickness of the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed metallization layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 10, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 9.
Chen does not explicitly disclose wherein the thickness of the conductive feature is greater than a sum of the thickness of the uppermost metallization layer of the first interconnect structure and the thickness of the uppermost metallization layer of the second interconnect structure.
However, Chen/Kao discloses wherein the thickness of the conductive feature 240 (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the thickness of the uppermost metallization layer of the second interconnect structure 320 (Chen, thickness of conductive feature 240 is greater than a thickness of a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the uppermost metallization layer of the second interconnect structure 320, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, sum of the thickness of the uppermost metallization layer of the first interconnect structure and the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Claim 11, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 8.
Chen/Kao discloses further comprising a second through-substrate via (Chen, plurality of vias 320 are a second through-substrate via, hereinafter, second through-substrate via 320, [0124], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) penetrating second substrate 310 (Chen, second through-substrate via 320 penetrates the second substrate 310, [0124], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), wherein the second through-substrate via 320 electrically connects the second interconnect structure 320 to the second bonded structure 340 (Chen, second through-substrate via 320 electrically connects the second interconnect structure 320 to the second bonded structure 340, [0124], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 12, Chen/Kao discloses the semiconductor package structure (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 8.
Chen/Kao discloses further comprising a redistribution layer (RDL) (Chen, interconnect structure 220 is a redistribution layer (RDL), hereinafter, RDL 220, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) disposed on the second side 131b” of the first substrate 131 (Chen, RDL 220 is disposed on the second side 131b” of the first substrate 131, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), wherein the RDL 220 comprises:
at least a metallization layer (Chen, metallization layer 224 is as least a metallization layer, hereinafter, metallization layer of the RDL 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
a top dielectric layer (Chen, protection layer 250 is a top dielectric layer, hereinafter, top dielectric layer 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the metallization layer 224 (Chen, top dielectric layer 250 is over the metallization layer 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A),
wherein the conductive feature 240 is disposed in the top dielectric layer 250 and electrically connected to the metallization layer 224 (Chen, conductive feature 240 is disposed in the top dielectric layer 250 and electrically connected to the metallization layer 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 13, Chen discloses a method for forming a semiconductor package structure (semiconductor structure P1, circuit element 300, and substrate 500 form a semiconductor package structure, hereinafter, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46), comprising:
receiving a first semiconductor component (integrated circuit component 130A is a first semiconductor component, hereinafter, first semiconductor component 130A, [0071], Figs. 14 and 46) having a first substrate (semiconductor substrate 131 is a first substrate, hereinafter, first substrate 131, [0057], Figs. 14 and 46) and a first interconnect structure (interconnect structure 132 is a first interconnect structure, hereinafter, first interconnect structure 132, [0057], Figs. 14 and 46) and a first bonding layer (redistribution circuit structure 160 is a first bonding layer, hereinafter, first bonding layer 160, [0123], Figs. 14 and 46), and receiving a second semiconductor component (core portion 310 and vias 320 are a second semiconductor component, hereinafter, second semiconductor component 310/320, [0123], Figs. 14 and 46) having a second substrate (second semiconductor component 310/320 includes a substrate, hereinafter, second substrate 310, [0123], Figs. 14 and 46) and a second interconnect structure (second semiconductor component 310/320 includes a second interconnect structure, hereinafter, second interconnect structure 320, [0123], Figs. 14 and 46) and a second bonding layer (redistribution circuit structure 340 is a second bonding layer, hereinafter, second bonding layer 340, [0123], Figs. 14 and 46);
bonding the first bonding layer 160 to the second bonding layer 340 to form a first bonded structure (redistribution circuit structures 160/330 form a first bonded structure, hereinafter, first bonded structure 160/330, [0123], Figs. 14 and 46) between the first interconnect structure 132 and the second interconnect structure 320 (first bonded structure 160/330 is between the first interconnect structure 132 and the second interconnect structure 320, [0123], Figs. 14 and 46);
forming a first through-substrate via (conductive vias 136 are through semiconductor vias and the through semiconductor via on the left-hand side (i.e. (-) X-direction) is the first through-substrate via, hereinafter, first through-substrate via 136L, [0040], Figs. 14 and 46) penetrating the first substrate 131 (first through-substrate via 136L penetrates the first substrate 131, [0040], Figs. 14 and 46);
forming a redistribution layer (RDL) (interconnect structure 220 is a redistribution layer (RDL), hereinafter, RDL 220, [0054], Figs. 14 and 46) over the first through-substrate via 136L (RDL 220 is formed over the first through-substrate via 136L, [0054], Figs. 14 and 46); and
forming a pad (connecting pads 230 is a pad, hereinafter, pad 230, [0057], Figs. 14 and 46) over the RDL 220 (pad 230 is formed over the RDL 220, [0057], Figs. 14 and 46).
Chen does not explicitly disclose forming a first through-substrate via penetrating the first substrate after the bonding of the first bonding layer to the second bonding layer
However, Kao discloses forming a first through-substrate via (Chen, first through-substrate via 136L, [0040], Figs. 14 and 46; Kao, first through-substrate via 104, [0053], Fig. 8A) penetrating the first substrate 131 (first through-substrate via 136L penetrates the first substrate 131, [0040], Figs. 14 and 46) after the bonding of the first bonding layer to the second bonding layer (Chen, first through-substrate via 136L, [0040], Figs. 14 and 46; Kao, first through-substrate via 104 penetrates the first substrate 108 after bonding the first bonding layer 806 to the second bonding layer 830, [0058], Fig. 8A). The combination to utilize a through-substrate via after bonding adjacent bonding layers as it ensures for proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a through-substrate via after bonding adjacent bonding layers to ensure for proper utilization of a through substrate via to enable 3D stacking of 2D integrated circuits (Kao, [0002]).
Claim 14, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 13.
Chen discloses further comprising:
forming a second through-substrate via (Chen, plurality of vias 320 are a second through-substrate via, hereinafter, second through-substrate via 320, [0124], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) penetrating second substrate 310 (Chen, second through-substrate via 320 penetrates the second substrate 310, [0124], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
forming a third bonding layer (Chen, redistribution circuit structures 330 form a third bonding layer, hereinafter, third bonding layer 330, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the second through-substrate via 320 (Chen, redistribution circuit structures 330 form a third bonding layer, hereinafter, third bonding layer 330 is formed over the second through-substrate via 320, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 15, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 14.
Chen/Kao discloses further comprising:
receiving a third semiconductor component (Chen, substrate 500 is a third semiconductor component and includes metallization layers 530, hereinafter, third semiconductor component 500/530, [0119], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) having a third substrate (Chen, third semiconductor component 500 includes a third substrate 500, [0119], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), a third interconnect structure (Chen, third semiconductor component 500/530 includes conductive terminals 400, contact pads 510, metallization layers 530 form a third interconnect structure 400/510/530, hereinafter, third interconnect structure 400/510/530, [0119], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) and a fourth bonding layer (Chen, solder mask layer 352a and bonding pads 354a are a fourth bonding layer, hereinafter, fourth bonding layer 352a/354a, [0130], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
bonding the third bonding layer 330 to the fourth bonding layer 352a/354a to form a second bonded structure (Chen, second bonded structure 330/352a/354a is formed while bonding the third bonding layer 330 to the fourth bonding layer 352a/354a, [0130], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 16, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 15.
Chen/Kao discloses wherein the first through-substrate via 136 is formed after the forming of the second bonded structure 330/352a/354a (Chen, first semiconductor component 130A is formed independently of the forming of the second bonded structure 330/352a/354a, wherein the first through-substrate via 136 is formed after the forming of the second bonded structure 330/352a/354a, Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 17, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 16.
Chen/Kao discloses wherein the forming of the RDL 220 comprises:
forming a first dielectric structure (Chen, dielectric layers 222 are a first dielectric structure, hereinafter, first dielectric structure 222, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the first through-substrate via 136 (Chen, first dielectric structure 222 are formed over the first through-substrate via 136, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A);
forming a metallization layer (Chen, metallization layer 224 is as least a metallization layer, hereinafter, metallization layer of the RDL 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) in the first dielectric structure 222 (Chen, metallization layer of the RDL 224 is formed in the first dielectric structure 222, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A);
forming a second dielectric structure (Chen, protection layer 250 is a second dielectric structure, hereinafter, second dielectric structure 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the metallization layer 224 (Chen, second dielectric structure 250 is formed over the metallization layer 224, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
forming a conductive feature in the second dielectric structure 250 (Chen, conductive feature 240 is formed in the second dielectric structure 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Claim 18, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 13.
Chen discloses wherein each of the first interconnect structure 132 and the second interconnect structure 400/510/530 comprises an uppermost metallization layer (Chen, first interconnect structure 132 includes protection layer 135, connecting pads 133, and plurality of connecting vias 134 which form an uppermost metallization layer, hereinafter, uppermost metallization layer of the first interconnect structure 133/134/135, [0021], Figs. 14 and 46; second interconnect structure 400/510/530 includes a solder mask layer 352b and a plurality of bonding pads 354b which form an uppermost metallization layer, hereinafter, uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Chen does not explicitly disclose a thickness of the conductive feature is greater than a thickness of the uppermost metallization layer of the first interconnect structure, and greater than a thickness of the uppermost metallization layer of the second interconnect structure.
However, Chen discloses a thickness of the conductive feature (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the first interconnect structure 133/134/135, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A), and greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b (Chen, thickness of conductive feature 240 is greater than a thickness of the uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, thickness of the uppermost metallization layer of the first interconnect structure, and thickness of the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed metallization layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 19, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 18.
Chen does not explicitly disclose wherein the thickness of the conductive feature is greater than a sum of the thickness of the uppermost metallization layer of the first interconnect structure and the thickness of the uppermost metallization layer of the second interconnect structure.
However, Chen discloses wherein the thickness of the conductive feature 240 (Chen, thickness of conductive feature 240, [0057], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) is greater than a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the thickness of the uppermost metallization layer of the second interconnect structure 352b/354b (Chen, thickness of conductive feature 240 is greater than a thickness of a sum of the thickness of the uppermost metallization layer of the first interconnect structure 133/134/135 and the uppermost metallization layer of the second interconnect structure 352b/354b, [0133], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of metallization layer thickness (i.e. thickness of the conductive feature, sum of the thickness of the uppermost metallization layer of the first interconnect structure and the uppermost metallization layer of the second interconnect structure) (result effective at least insofar as controlling line-widths and/or even profiles of metallization layers and subsequent conductive feature (i.e. via interposed between the TSV and pad) thicknesses results in improved line/wiring reliability with controlled pitch and width (Chen, [0066])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed metallization layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 20, Chen/Kao discloses the method (Chen, semiconductor package structure P1/300/500, [0123], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) of claim 13.
Chen discloses wherein the forming of the pad 230 comprises:
forming a passivation structure (Chen, protection layer 250 is a passivation structure, hereinafter, passivation structure 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A) over the conductive feature 240 (Chen, passivation structure 250 is formed over the conductive feature 240, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A); and
forming the pad 230 in the passivation structure 250 (Chen, pad 230 is formed in the passivation structure 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A),
wherein a portion of the pad 230 is exposed through the passivation structure 250 (Chen, a portion of the pad 230 is exposed through the passivation structure 250, [0054], Figs. 14 and 46; Kao, three-dimensional integrated circuit 800A, [0053], Fig. 8A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kao (US 2021/0320052 A1) discloses a semiconductor package structure (cross-sectional view 800B of three-dimensional integrated circuit (3D IC) is a semiconductor package structure, hereinafter, semiconductor package structure 800B, [0053], Fig. 8B) comprising:
a first semiconductor component (first IC chip 802 is a first semiconductor component, hereinafter, first semiconductor component 802, [0053], Fig. 8B) having a first substrate (first semiconductor component 802 includes first substrate 108, [0053], Fig. 8B) and a first interconnect structure (first semiconductor component 802 includes a first interconnect structure 116, [0053], Fig. 8B), wherein the first interconnect structure 116 is disposed on a first side of the first substrate 108 (first interconnect structure 116 is disposed on a first side (i.e. frontside 108fs) of the first substrate 108, [0053], Fig. 8B);
a second semiconductor component (second IC chip 804 is a second semiconductor component, hereinafter, second semiconductor component 804, [0055], Fig. 8B) having a second substrate (second semiconductor component 804 includes a second substrate 808, [0055], Fig. 8B) and a second interconnect structure (second semiconductor component 804 includes a second interconnect structure 810, [0055], Fig. 8B);
a bonded structure between and bonded to the first interconnect structure 116 and the second interconnect structure 810 (bond interface 828 is the region bonding the first interconnect structure 116 and the second interconnect structure 810 to each other is a bonded structure, hereinafter, bonded structure 828, [0058], Fig. 8B);
a first through-substrate via (TSV 104 is a first through-substrate via, hereinafter, first through-substrate via 104, [0054], Fig. 8B) penetrating the first substrate 108 from a second side 108bs to the first side 108fs (first through-substrate via 104 penetrates the first substrate 108 from a second side 108bs to the first side 108fs, [0054], Fig. 8B), wherein the second side 108fs is opposite to the first side 108bs (second side 108fs is opposite to the first side 108bs, [0054], Fig. 8B);
a pad (contact pad 112c is a pad, hereinafter, pad 112c, [0059], Fig. 8B) disposed over the second side 108bs of the first substrate 108 (pad 112c is disposed over the second side 108bs of the first substrate 108, [0059], Fig. 8B); and
a conductive feature (via 832 is a conductive feature, hereinafter, conductive feature 832, [0059], Fig. 8B) disposed over the second side 108bs of the first substrate 108 (conductive feature 832 is disposed over the second side 108bs of the first substrate 108, [0059], Fig. 8B) and between the first through-substrate via 104 and the pad 112c (conductive feature 832 is disposed between the first through-substrate via 104 and the pad 112c, [0059], Fig. 8B),
wherein the conductive feature 832 electrically connects the first through-substrate via 104 to the pad 112c (conductive feature 832 electrically connects the first through-substrate via 104 to the pad 112c, [0060], Fig. 8B), and the conductive feature 832 is electrically connected to the first interconnect structure 116 by the first through-substrate via 104 (conductive feature 832 is electrically connected to the first interconnect structure 116 by the first through-substrate via 104, [0060], Fig. 8B).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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