DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species 8, Fig. 9, claims 17-36 in the reply filed on July 2, 2026 is acknowledged. However, after inspection, claims 20, 26, 29, 30 and 32 do not belong to the elected Species. It seems that claim 20 reads on non-elected Species 9, Fig. 10. Claim 26 reads on Species 1 and 2. Claims 29, 30 and 32 read on non-elected species 1, Figs. 3A-3H. Claims 20, 26, 29, 30 and 32 have been withdrawn. Claims 17-19, 21-25, 27, 28, 31 and 33-36 will be examined. Claims 1-16 have been cancelled by the Applicant. Action on the merits is as follows:
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 33 and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 33 recites the limitation "”the interposer" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination the Examiner has taken “a second interposer” in claim 33, and “the second interposer” in claim 34 to be “an interposer” and “the interposer” The Examiner has done this in order to make sure the claims read on the Applicant’s elected species. The recitation “a second interposer” and “the interposer” implies that there is a first interposer. Claim 34 inherits this deficiency due to the dependency upon claim 33. Appropriate correction is required.
Claims 23, 24, 28, 33 and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 23 recites the limitation "”the logic die" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 24 recites the limitation "”the logic die" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 28 recites the limitation "”the logic die" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 33 recites the limitation "”the logic die" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner has taken “the logic die” to be “the logic device”. Claim 34 inherits these deficiencies due the dependency upon claim 33. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17, 21 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (Lin) (US 2021/0375781 A1).
In regard to claim 17, Lin (Figs. 2K, 14-21 and associated text) discloses a method for forming a package structure (Fig. 2K), comprising: forming a logic device (item 208) over a substrate (item 104); forming a first interconnect structure (items 132 or 136, paragraphs 19, 34) on a front-side surface of the logic device (item 104); forming a second interconnect structure (items 132 or 136, paragraphs 19, 34) on a back-side surface of the logic device (item 104); and bonding a memory device (item 240, paragraph 48) on the first interconnect structure (items 132 or 136, paragraphs 19, 34) by a hybrid bonding structure (items 130 plus 246 plus 236) to form a die (item 200k), wherein the hybrid bonding structure (items 130 plus 246) includes a metal-to-metal bonding (item 236) and a non- metal-to-non-metal bonding (items 130, 246).
In regard to claim 21, Lin (Figs. 2K, 14-21 and associated text) discloses wherein the logic device (item 104) comprises a plurality of nanostructure (nanosheets, nanowire, paragraph 35), and a gate structure (item 210) formed on the nanostructure (nanosheets, nanowire, paragraph 35).
In regard to claim 22, Lin (Figs. 2K, 14-21 and associated text) discloses further comprising: forming a contact structure (item 234) over the gate structure (item 210); and forming the first interconnect structure (item 132) on the contact structure (item 234).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Lin) (US 2021/0375781 A1) in view of Mathuriya et al. (Mathuriya) (US 12,079,475 B1).
In regards to claim 18, Lin (Fig. 2A-2K and associated text) discloses further comprising: bonding the logic device (item 208) to a wafer (item 102), wherein the wafer is below the second interconnect structure (item 110), but does not specifically disclose further comprising: bonding the logic device to an interposer, and forming a package layer surrounding the memory device.
Mathuriya (Fig. 5A and associated text) discloses bonding the logic device (item 506) to an interposer (item 302), and forming a package layer (item 318) surrounding the memory device (item 507).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Mathuriya for the purpose of the electrical connection and protection.
Claim(s) 19, 23-25, 27, 28, 31 and 33-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Lin) (US 2021/0375781 A1) in view of Marin et al. (Marin) (US 2024/0128247 A1).
In regards to claim 19, Lin (Fig. 2A-2K and associated text) discloses a substrate (item 102) under the second interconnect (items 132 or 136, paragraphs 19, 34), but does not specifically disclose further comprising: forming an optical device below the second interconnect structure.
Marin (Fig. 1 and associated text) discloses an interposer structure (items 116 plus 112) comprised of optical devices (items 126, 114, paragraph 42) within an interconnect structure (items 112 plus 114 plus 126) with through-substrate via (TSV) structures (item 118) below the optical devices (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias).
Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses forming an optical device (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin) below the second interconnect structure (items 132 or 136, paragraphs 19, 34, Lin).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Marin for the purpose of optical connectivity (paragraphs 34, 36, 42).
In regards to claim 23, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses further comprising: bonding the logic (die) device (item 208, Lin, item 122, paragraph 32, Marin) to an interposer (item 102, Lin, items 116 plus 112, Marin), wherein the interposer (item 102, Lin, items 116 plus 112, Marin) comprises waveguides (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin) formed in an interconnect structure (items 112 plus 114 plus 126, Marin).
In regards to claim 24, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses further comprising: forming an optical device (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin) below the logic (die) device (item 208, Lin, item 122, paragraph 32, Marin).
In regards to claim 25, Lin (Fig. 2A-2K and associated text) discloses a method for forming a package structure (Figs. 2A-2K), comprising: forming a logic device (item 208) over a substrate (item 104), wherein the logic device (item 208) comprises a gate structure (item 210) and an S/D structure (item 214); forming a first interconnect structure (items 132 or 136, paragraphs 19, 34) on a front-side surface of the logic device (item 208); forming a first substrate (item 102) on the first interconnect structure (items 132 or 136, paragraphs 19, 34); forming a second interconnect structure (items 132 or 136, paragraphs 19, 34) on a back-side surface of the logic device (item 208); and bonding a memory device (items 110, 134 or 240, paragraphs 34, 48) on the first substrate (item 102), but does not specifically disclose forming a first interposer on the first interconnect structure, wherein the first interposer comprises through-substrate via (TSV) structures;
Marin (Fig. 1 and associated text) discloses an interposer structure (items 116 plus 112) comprised of optical devices (items 126, 114, paragraph 42) within an interconnect structure (items 112 plus 114 plus 126) with through-substrate via (TSV) structures (item 118) below the optical devices (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias).
Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses forming a first interposer (item 102, Lin, items 116 plus 112, Marin) on the first interconnect structure (items 132 or 136, paragraphs 19, 34, Lin), wherein the first interposer (item 102, Lin, items 116 plus 112, Marin) comprises through-substrate via (TSV) structures (item 118, Marin).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Marin for the purpose of electrical and/or optical connectivity (paragraphs 34, 36, 42).
In regards to claim 27, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses further comprising: removing the substrate (item 104, Lin) to expose the S/D structure (item 214, paragraph 72, Lin).
In regards to claim 28, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses further comprising: bonding the logic (die) device (item 208, Lin, item 122, paragraph 32, Marin) to an interposer (item 102, Lin, items 116 plus 112, Marin), wherein the interposer (item 102, Lin, items 116 plus 112, Marin) comprises waveguides (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin) formed in an interconnect structure (items 112 plus 114 plus 126, Marin).
In regards to claim 31, Lin (Fig. 2A-2K and associated text) discloses a method for forming a package structure (Figs. 2A-2K), comprising: forming a logic device (item 208) over a substrate (item 104); forming a first interconnect structure (items 132 or 136, paragraphs 19, 34) on a front-side surface of the logic device (item 208); removing the substrate (item 104, paragraph 72) to expose a portion of the logic device (item 208); forming a second interconnect structure (items 132 or 136, paragraphs 19, 34) on the exposed portion of the logic device (item 208); bonding a memory device (items 110, 134 or 240, paragraphs 34, 48) over the first interconnect structure (items 132 or 136, paragraphs 19, 34), but does not specifically disclose forming an optical device below the second interconnect structure (items 132 or 136, paragraphs 19, 34).
Marin (Fig. 1 and associated text) discloses an interposer structure (items 116 plus 112) comprised of optical devices (items 126, 114, paragraph 42) within an interconnect structure (items 112 plus 114 plus 126) with through-substrate via (TSV) structures (item 118) below the optical devices (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Marin for the purpose of electrical and/or optical connectivity (paragraphs 34, 36, 42).
In regards to claim 33, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses further comprising: bonding the logic (die) device (item 208, Lin, item 122, paragraph 32, Marin) to (a second) an interposer (item 102, Lin, items 116 plus 112, Marin), wherein the (second) interposer (item 102, Lin, items 116 plus 112, Marin) comprises waveguides (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin) formed in an interconnect structure (items 112 plus 114 plus 126, Marin).
In regards to claim 34, Lin (Fig. 2A-2K and associated text) as modified by Marin (Fig. 1 and associated text) discloses wherein the (second) interposer (item 102, Lin, items 116 plus 112, Marin) comprises through-substrate via (TSV) structures (item 118, Marin) below the waveguides (items 126, 114, paragraphs 34, 42, optical waveguides, fiber, splitters, combiners, couplers, vias, Marin).
In regard to claim 35, Lin (Figs. 2K, 14-21 and associated text) discloses wherein the logic device (item 104) comprises a plurality of nanostructure (nanosheets, nanowire, paragraph 35), and a gate structure (item 210) formed on the nanostructure (nanosheets, nanowire, paragraph 35).
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Lin) (US 2021/0375781 A1) in view of Marin et al. (Marin) (US 2024/0128247 A1) as applied to claims 19, 23-25, 27, 28, 31 and 33-35 above, and further in view of Wang et al. (Wang) (US 2014/0206140 A1).
In regards to claim 36, Lin as modified by Marin does not specifically disclose forming a first package layer surrounding the memory device; and forming a second package layer surrounding the optical device, wherein an interface between the first package layer and the second package layer is aligned with a sidewall surface of the optical device.
Wang (Fig. 9 and associated text) discloses forming a first package layer (item 16) surrounding the top die (item 10, equivalent to memory device); and forming a second package layer (item 24) surrounding the second/bottom die (item 14, equivalent to optical device), wherein an interface (item 28) between the first package layer (item 16) and the second package layer (item 24) is aligned with a sidewall surface of the optical device (item 14).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Wang for the purpose of protection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 July 16, 2026
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