DETAILED ACTION
This action is responsive to the application No. 18/413,376 filed on January 16, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Group I invention in the reply filed on 05/11/2026 is acknowledged. The Applicants indicated that claims 1-11 read on the elected invention. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Oh (US 2025/0107073).
Regarding Claim 1, Oh (see, e.g., Fig. 3), teaches a semiconductor structure, comprising:
a substrate 110, including a plurality of fin structures ACT1 (see, e.g., pars. 0023, 0025);
a dielectric layer 116, disposed over adjacent fin structures ACT1, wherein a top surface of the dielectric layer 116 is a substantially planar surface (see, e.g., par. 0029);
a bit line structure BL, disposed over the substrate 110 and between adjacent fin structures ACT1, wherein the bit line structure BL includes a polysilicon layer 132 contacting the top surface of the dielectric layer 116 (see, e.g., pars. 0034, 0037); and
a spacer structure 150, surrounding the bit line structure BL, wherein the spacer structure 150 contacts the top surface of the dielectric layer 116 (see, e.g., par. 0050).
Regarding Claim 2, Oh teaches all aspects of claim 1. Oh (see, e.g., Fig. 3), teaches that a bottom surface of an inner nitride layer 152 of the spacer structure 150 is substantially planar (see, e.g., par. 0050).
Regarding Claim 3, Oh teaches all aspects of claim 1. Oh (see, e.g., Fig. 3), teaches that that the bit line structure BL further comprises:
a first metal layer 134, stacked over the polysilicon layer 132 (see, e.g., par. 0037);
a second metal layer 136, stacked over the first metal layer 134 (see, e.g., par. 0034); and
a nitride layer 140, stacked over the second metal layer 136 (see, e.g., par. 0049).
Regarding Claim 4, Oh teaches all aspects of claim 3. Oh (see, e.g., Fig. 3), teaches that a sidewall of the polysilicon layer 132 is substantially aligned with a sidewall of the first metal layer 134, the second metal layer 136 or the nitride layer 140 along a vertical direction Z (see, e.g., Fig. 3).
Regarding Claim 5, Oh teaches all aspects of claim 3. Oh (see, e.g., Fig. 3), teaches that the first metal layer 134 includes titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten silicon (WSi), or a combination thereof (see, e.g., par. 0037).
Regarding Claim 7, Oh teaches all aspects of claim 1. Oh (see, e.g., Fig. 3), teaches that the polysilicon layer 132 is a layer of undoped polysilicon (see, e.g., par. 0037).
Regarding Claim 8, Oh teaches all aspects of claim 1. Oh (see, e.g., Fig. 3), teaches that a sidewall of the bit line structure BL is substantially straight (see, e.g., Fig. 3).
Regarding Claim 9, Oh teaches all aspects of claim 1. Oh (see, e.g., Fig. 3), teaches that the spacer structure 150 comprises:
a first nitride layer 152, proximal to a sidewall of the bit line structure BL (see, e.g., par. 0050);
a second nitride layer 156, surrounding the first nitride layer 152 (see, e.g., par. 0050); and
an oxide layer 154, disposed between the first nitride layer 152 and the second nitride layer 156 (see, e.g., par. 0050).
Regarding Claim 10, Oh teaches all aspects of claim 9. Oh (see, e.g., Fig. 3), teaches that a bottom surface of the first nitride layer 152 contacts the top surface of the dielectric layer 116.
Regarding Claim 11, Oh teaches all aspects of claim 10. Oh (see, e.g., Fig. 3), teaches that the second nitride layer 156 extends below the bottom surface of the first nitride layer 152 (see, e.g., Fig. 3).
Claims 1, 3, and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park (US 2025/0072087).
Regarding Claim 1, Park (see, e.g., Figs. 1-3), teaches a semiconductor structure, comprising:
a substrate 100, including a plurality of fin structures ACT (see, e.g., pars. 0020-0021);
a dielectric layer BP, disposed over adjacent fin structures ACT, wherein a top surface of the dielectric layer BP is a substantially planar surface (see, e.g., par. 0030);
a bit line structure BL/OP/(PP, DC), disposed over the substrate 100 and between adjacent fin structures ACT, wherein the bit line structure BL/OP/(PP, DC) includes a polysilicon layer PP contacting the top surface of the dielectric layer BP (see, e.g., pars. 0031, 0034); and
a spacer structure SPC, surrounding the bit line structure BL/OP/(PP, DC), wherein the spacer structure SPC contacts the top surface of the dielectric layer BP (see, e.g., par. 0040).
Regarding Claim 3, Park teaches all aspects of claim 1. Park (see, e.g., Figs. 1- 3), teaches that that the bit line structure BL/OP/(PP, DC) further comprises:
a first metal layer OP, stacked over the polysilicon layer PP (see, e.g., par. 0035);
a second metal layer BL, stacked over the first metal layer OP (see, e.g., par. 0033); and
a nitride layer BCP, stacked over the second metal layer BL (see, e.g., par. 0036).
Regarding Claim 6, Park teaches all aspects of claim 3. Park (see, e.g., Figs. 1-3), teaches that the second metal layer BL includes tungsten (W) (see, e.g., par. 0033).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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