DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu (US 20130045562), hereinafter Liu.
Regarding claim 1, Liu (US 20130045562) teaches a method for fabricating a semiconductor device, comprising:
providing a substrate (structure shown in Figure 2);
forming (in the step of Figure 3) a catalytic conductive layer (20) on the substrate and patterning (by using 14, 15) the catalytic conductive layer (20) to form an opening exposing an exposed portion of the substrate (e.g. part 15 of substrate structure shown in Figure 2 is exposed in Figure 3), while leaving a covered portion (i.e. portion where 20 is shown present in Figure 3) of the substrate covered by the catalytic conductive layer (para 48 discloses "metal nanoparticles 20, which serve as a catalyst in forming openings within the single-crystalline silicon substrate 10, can be comprised of Pt, Ag, Au, Pd, Rh, Ru, Ir, Os, Mo or Ni");
performing a trench-etching process (in step of Figure 4) to recess (by creating 19 described as “wall portions” of “the substrate”) the covered portion (compare Figures 3 and 4) of the substrate, resulting in a first trench;
removing the catalytic conductive layer (20 is shown removed in step of Figure 5; see para 51, 1st sentence); and
forming an isolation layer in the first trench (24, see Figure 6 and para 55);
wherein performing the trench-etching process comprises applying an etchant solution to the catalytic conductive layer (20) and the substrate (i.e. to part 10A of substrate).
Regarding claims 2-3, Liu teaches the method for fabricating the semiconductor device of claim 1, wherein (as recited in claim 3) the catalytic conductive layer comprises silver (para 48, 1st sentence discloses 20 may comprise “Ag”; i.e. silver); AND wherein (as recited in claim 3) the substrate comprises silicon (described as "single-crystalline silicon substrate" in para 53).
Regarding claims 5-7, Liu teaches the method for fabricating the semiconductor device of claim 1, wherein performing the trench-etching process comprises: applying an etchant to the catalytic conductive layer and the substrate; wherein the etchant comprises an oxidant and an acid (para 53), wherein (as recited in claim 6) the oxidant comprises hydrogen peroxide, potassium permanganate, nitric acid, silver nitrate, or sodium persulfate (para 53 describes etchant comprising “HNO3”; i.e. nitric acid); OR wherein (as recited in cliam 7), the acid comprises hydrofluoric acid, or nitric acid (para 53 describes etchant as comprising “HF”; i.e. hydrofluoric acid)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li (US 20180090336), hereinafter Li.
Regarding claims 4 and 8-18, Liu teaches the method for fabricating the semiconductor device but does not teach the limitations recited in claim 8-18.
However, these process details of vapor etching are known in the art. Li (US 20180090336) describes in para 22 that titanium nitride may be used in a vapor-phase chemical etching process using an oxidant and an acid, such as hydrogen peroxide and hydrofluoric acid with vapor phase etchant comprising oxidant vapor and acid vapor (para 22), and for etching, the substrate may be heated to a temperature in a range from about 30° C to about 95° C (para 25, noting this overlaps with the claimed range), an increased etching temperature may enhance mass transfer during etching, thereby promoting forward etching and enabling the fabrication of higher aspect ratio etched features (para 25). Li further teaches the carrier gas used to transport the oxidant vapor and the acid vapor may be an inert carrier gas such as nitrogen, argon or helium (para 37). Still further, Li teaches he vapor-phase etchant may have a molar ratio of oxidant vapor to acid vapor in a range from about 0.02 to about 10 (para 41), which overlaps with the claimed range in claims 9 and 18. Li further teaches that when using vapor-phase etching, the etching duration may be from about 10 seconds to about 60 minutes (para 42), which overlaps with the range in claim 8. Li further teaches Li also teaches high aspect ratio etched features of up to hundreds of nanometers or even tens of microns in length can be obtained (para 42),
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Liu to include the limitations of claims 8-18 as taught by Li. The ordinary artisan would have been motivated to modify Liu for at least the purpose of optimizing typical process parameters for vapor etching (as explained above), thereby using vapor-phase etching to promote forward etching and enabling the fabrication of higher aspect ratio etched features (para 25 of Li), while achieving high aspect ratios as in claim 4.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892