DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 05 June 2026, with respect to the previous Office action have been fully considered and the responses set forth below.
Regarding the provisional double patenting rejection of Claims 4, 7, and 8 (Remarks p. 6-8) made in the previous Office action of 05/08/2026. Applicant has amended claim 4 to sufficiently distinguish from the claim 1 of co-pending application 18/797,585. Therefore, the provisional double patenting rejection of the previous Office action is withdrawn.
Regarding the 35 USC §112(b) rejection of claim 4 (Remarks; p. 8) made in the previous Office action of 05/08/2026. Applicant has amended claim 4 to overcome the issue previously outlined. Therefore, the §112(b) rejection of claim 4 made in the previous Office action is withdrawn.
Regarding the 35 USC §103 rejection of claim 1 (Remarks; p. 8-10) made in the previous Office action of 05/08/2026. Applicant has amended claim 1 to recite “wherein a top surface of each of the bit line structures is positioned above the top surface of the contact layer and the top surface of the liner layer”, and states “Examiner alleges that Zhang teaches the topmost surface of BL is higher than the top surface of …”.
This is not persuasive, as “topmost” has not been amended into the claim, nor is it required by the claim as presently presented. The claim has not been amended with sufficient specificity to overcome the prior art of record Zhang and Matsuura, as shown in view of the annotated figure provided below. It is suggested to recite limitation(s) properly defining the uppermost or topmost surfaces and their spatial relationship to the other respective features. The rejection has been
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updated below.
Regarding the 35 USC §103 Rejection of Claim 4 (Remarks; p. 11-12), Applicant submits that the prior art of record fails to teach or suggest the formation of a contact opening. However, the claim is directed toward a device, and device claims are not defined by their method of production. Therefore, considering the structural elements of the amended claim 4 in relation to the contact structure “formed” in the “contact opening”, Zhang discloses the following in reference to Fig. 1, 1A, 1B:
A contact opening (Zhang annotated Fig. 1A; OP) between the one of the bit line structures (BL) and one of the partition layers (104) (as shown in view of Fig. 1); … wherein the contact opening (OP) is formed to expose a top surface of the substrate (top of 1b which is an implant region of the active layer of substrate 100; ¶0026) to define a bottom of the contact opening thereat; wherein the cell contact structure (Zhang 134/136 modified by Matsuura to include a polysilicon liner 72) is disposed in the contact opening (134/136 including modified 72 is disposed in OP), such that the bottom of contact opening (bottom of OP) is positioned below the top surface of the contact layer (134/136) and the top surface of the liner layer (72) (as shown by Annotated Zhang Fig. 1A); wherein a top surface of each of the bit line structures (BL) is positioned above the top surface of the contact layer and the top surface of the liner layer (as shown in view of Annotated Zhang Fig. 1B above).
Therefore, the rejection is maintained and updated below in view of the newly presented amendments.
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Regarding Applicant’s submission that there “must be something in the reference that suggests the combination” (Remarks; p. 14) in relation to the combination of Zhang and Matsuura. This is not persuasive, as the contact structure of Zhang (134/136) includes TiN/W, respectively contacting an underlying semiconductor layer (130). Matsuura teaches surrounding a TiN/W contact (71/70, respectively) with a doped polysilicon layer (72) in order to reduce contact resistance (Matsuura; ¶0126) with the underlying semiconductor layer (EP). Matsuura provides evidence (of record; Matsuura; ¶0126) to why one of ordinary skill in the art would make such a modification, and therefore the combination is proper and the rejection is maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Janbo Zhang et al. (US 20210375878 A1; hereinafter Zhang) in view of Osamu Matsuura et al. (US 20200083249 A1; hereinafter Matsuura).
Regarding Claim 1, Zhang discloses a cell contact structure (Fig. 1, Fig. 1A, Fig. 1B) (106; ¶0029), comprising:
a contact layer (134/136; ¶0029) positioned on a substrate (100; ¶0020) and enclosed by a plurality of bit line structures (BL; ¶0021) and a plurality of partition layers (104; ¶0022); and
wherein the contact layer (134/136) comprises tungsten, titanium, or titanium nitride (as described in ¶0029).
Zhang is silent regarding wherein the cell contact structure (106) further comprises:
a liner layer positioned between the contact layer (134/136) and the substrate (100), between the contact layer (134/136) and the plurality of bit line structures (BL), and between the contact layer (134/136) and the plurality of partition layers (104);
wherein a top surface of the contact layer (134/136) and a top surface of the liner layer are substantially coplanar;
wherein a top surface of each of the bit line structures (BL) is positioned above the top surface of the contact layer and the top surface of the liner layer
wherein the liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium.
In the same field of endeavor, Matsuura (Fig. 7) teaches a contact structure (CS; ¶0123) contacting a semiconductor layer (EP; ¶0119-¶0121) (equivalent to semiconductor layer 130 of Zhang) which provides electrical contact to impurity regions in the substrate (PP1/PP2; ¶0093) (equivalent to 1b of Zhang); wherein Matsuura’s contact structure comprises:
a liner layer (72; ¶0124) surrounding a contact layer (70/71 comprising TiN and W, respectively, which are the same respective materials used by Zhang for 134/136),
wherein a top surface of the contact layer (70/71) and a top surface of the liner layer (72) are substantially coplanar (as shown in Matsuura Fig. 7);
wherein the liner layer (72) comprises doped polycrystalline silicon (¶0125), doped polycrystalline germanium, or doped polycrystalline silicon germanium.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the doped polycrystalline liner layer of Matsuura (72) surrounding the bottom and sides of the contact layer of Zhang (134/136) in order to reduce the contact resistance between the contact layer and the underlying semiconductor layer (as described in ¶0126 of Matsuura).
This modification would result in Matsuura’s doped polysilicon liner (72) surrounding the contact layer (134/136) of Zhang, thereby satisfying the above limitations, including wherein top surfaces of the contact layer (Zhang; 134/136) and liner layer (72 as modified by Matsuura) are coplanar (they are coplanar at indicated position in the annotated Zhang Fig. 1B provided above), and a top surface of the bit line structures (BL) are above this coplanar top surface, as shown in the annotated Zhang figure 1B. Furthermore, this modification is compatible because of the use of the same materials for the same features between the disclosures of Zhang and Matsuura (as noted above).
Regarding Claim 2, modified Zhang teaches the cell contact structure of claim 1, wherein the liner layer (Matsuura; 72) comprises n-type dopants or p-type dopants (Matsuura; ¶0125), wherein the liner layer (Matsuura; 72) is in contact with at least one of the partition layers (104) (as modified they are in thermal contact with one another).
Regarding Claim 4, Zhang discloses a semiconductor device (Fig. 1, Fig. 1A, Fig. 1B, annotated Zhang Fig. 1A, and annotated Zhang Fig. 1B provided above), comprising:
a substrate (100; ¶0020);
two bit line structures (BL/BL; ¶0021) may be formed on the substrate (100), extending along a first direction (D2), and separated from each other (as shown in Fig. 1);
two partition layers (104/104; ¶0022) positioned on the substrate (100), extending along a second direction (D1) perpendicular to the first direction, separated from each other, and simultaneously contacting the two bit line structures (BL/BL) (as shown in Fig. 1) to form a contact opening (Annotated Zhang Fig. 1A; OP) between the one of the bit line structures (BL) and one of the partition layers (104) (OP is diagonally between BL and 104 as shown in view of Fig. 1); and
a cell contact structure (106; ¶0029) comprising:
a contact layer (134/136; ¶0029) positioned on the substrate (100) and enclosed by the two bit line structures (BL/BL) and the two partition layers (104/104); and
wherein the contact opening (OP) is formed to expose a top surface of the substrate (top of 1b which is an implant region of the active layer of substrate 100; ¶0026) to define a bottom of the contact opening thereat (as labeled in Annotated Zhang Fig. 1A);
wherein the cell contact structure (106) is disposed in the contact opening (OP) (as shown in Annotated Zhang Fig. 1A), such that the bottom of contact opening (bottom of OP) is positioned below the top surface of the contact layer (any top surface of 134/136, as shown by Annotated Zhang Fig. 1A);
wherein a top surface of each of the bit line structures (a top surface of BL as indicated in Annotated Zhang Fig. 1B) is positioned above the top surface of the contact layer (the top surface of contact as indicated and shown in Annotated Zhang Fig. 1B);
wherein the contact layer (134/136) comprises tungsten, titanium, or titanium nitride (as described in ¶0029).
Zhang is silent regarding wherein the cell contact structure (106) further comprises:
a liner layer positioned between the substrate (100) and the contact layer (134/136), between the two bit line structures (BL/BL) and the contact layer (134/136), and between the two partition layer (104/104) and the contact layer (134/136);
wherein a top surface of the liner layer and a top surface of the contact layer (134/136) are substantially coplanar;
wherein the bottom of contact opening (bottom of OP) is positioned below the top surface of the liner layer; wherein a top surface of each of the bit line structures (BL) is positioned above the top surface of the liner layer;
wherein the liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium.
In the same field of endeavor, Matsuura (Fig. 7) teaches a contact structure (CS; ¶0123) contacting a semiconductor layer (EP; ¶0119-¶0121) (equivalent to semiconductor layer 130 of Zhang) which provides electrical contact to impurity regions in the substrate (PP1/PP2; ¶0093) (equivalent to 1b of Zhang); wherein Matsuura’s contact structure comprises:
a liner layer (72; ¶0124) surrounding a contact layer (70/71 comprising TiN and W, respectively, which are the same respective materials used by Zhang for 134/136),
wherein a top surface of the contact layer (70/71) and a top surface of the liner layer (72) are substantially coplanar (as shown in Matsuura Fig. 7);
wherein the liner layer (72) comprises doped polycrystalline silicon (¶0125), doped polycrystalline germanium, or doped polycrystalline silicon germanium.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the doped polycrystalline liner layer of Matsuura (72) surrounding the bottom and sides of the contact layer of Zhang (134/136) in order to reduce the contact resistance between the contact layer and the underlying semiconductor layer (as described in ¶0126 of Matsuura).
This modification would result in Matsuura’s doped polysilicon liner (72) surrounding the contact layer (134/136) of Zhang, thereby satisfying the above limitations, including wherein top surfaces of the contact layer (Zhang; 134/136) and liner layer (72 as modified by Matsuura) are coplanar (they are coplanar at indicated position in the annotated Zhang Fig. 1B provided above), wherein the bottom of contact opening (bottom of OP) is positioned below the top surface of the liner layer (72) (as indicated by Annotated Zhang Fig. 1A); and wherein a top surface of each of the bit line structures (top of BL as indicated in Annotated Zhang Fig. 1B) is positioned above the top surface of the liner layer (as indicated in Annotated Zhang Fig. 1B). Furthermore, this modification is compatible because of the use of the same materials for the same features between the disclosures of Zhang and Matsuura (as noted above).
Regarding Claim 5, modified Zhang teaches the semiconductor device of claim 4, wherein the liner layer (Matsuura; 72) comprises n-type dopants or p-type dopants (Matsuura; ¶0125), wherein the liner layer (72) is in contact with at least one of the partition layers (104) (as modified they are in thermal contact with one another).
Regarding Claim 6, modified Zhang teaches the semiconductor device of claim 4, wherein the contact layer (Zhang 106 which comprises 134/136) comprises a rectangular or square-shaped cross-sectional profile in a top-view perspective (as shown in Zhang Fig. 1).
Allowable Subject Matter
Claims 3 and 7-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art of record teaches the limitations of claim 1 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein a top surface of each of the partition layers is coplanar with the top surface of each of the bit line structures.
As shown in Zhang Fig. 1A and 1B, the bit lines structures (BL) and the partition structures (104) are not coplanar across the two figures. There is no description in the specification stating these features are coplanar, and the figures suggest they are not, since 134 (of the contact layer) appears to have a different thickness above the partition 104 in Fig. 1A than 134 does above the top of bit line (BL) in Fig. 1B. This reasonably suggest the bit line BL is lower than the partition structure 104.
Regarding Claim 7, the prior art of record teaches the limitations of claim 4 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein a top surface of each of the partition layers is coplanar with the top surface of each of the bit line structures.
As shown in Zhang Fig. 1A and 1B, the bit lines structures (BL) and the partition structures (104) are not coplanar across the two figures. There is no description in the specification stating these features are coplanar, and the figures suggest they are not, since 134 (of the contact layer) appears to have a different thickness above the partition 104 in Fig. 1A than 134 does above the top of bit line (BL) in Fig. 1B. This reasonably suggest the bit line BL is lower than the partition structure 104.
Regarding Claim 8, the prior art of record teaches the limitations of claim 1 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein a top surface of each of the spacer structures, the top surface of each of the partition layers, and the top surface of each of the bit line structures are coplanar with each other.
As shown in Zhang Fig. 1A and 1B, at least the bit lines structures (BL) and the partition structures (104) are not coplanar across the two figures. There is no description in the specification stating these features are coplanar, and the figures suggest they are not, since 134 (of the contact layer) appears to have a different thickness above the partition 104 in Fig. 1A than 134 does above the top of bit line (BL) in Fig. 1B. This reasonably suggest the bit line BL is lower than the partition structure 104.
For at least this reason claims 9-20 would also be allowable based on their dependency from claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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