DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species III, directed to FIGS. 7A and 7B in the reply filed on November 21, 2025 is acknowledged.
Applicant alleges that claims 1-20 are directed to the elected species.
Applicant’s independent claim 7 requires “wherein a fin number of each of the first fin transistors in the first logic cells is greater than a fin number of each of the second fin transistors in the second logic cells” in the claim language.
Applicant’s elected species III, FIG. 7A, shows that Logic cell 30B_1 and Logic cell 20A_1 with a fin number of each of the first fin transistors in the first logic cells (FIG. 7, item 30B_1) has the same fin number as a fin number of each of the second fin transistors in the second logic cells (FIG. 7A, item 20A_1).
Claim 7 reads upon non-elected Species I. FIGS. 4A and 4B, and Species II. FIG. 5.
Claims 7-11 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 21, 2025.
Information Disclosure Statement
The information disclosure statement filed January 16, 2024 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
There is no copy of Japanese Patent JP 2014-236116 attached.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the wherein a sum of lengths of the one of the first logic cells and the one of the third logic cells is substantially equal to a sum of lengths of the two adjacent second logic cells in claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 18. Claim 18 recites the limitation “wherein the dielectric material comprises a plurality of segments parallel to each other.” in the claim language.
Regarding claim 20. Claim 20 recites the limitation “wherein a sum of lengths of the one of the first logic cells and the one of the third logic cells is substantially equal to a sum of lengths of the two adjacent second logic cells” in the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 20. Claim 20 recites the limitation “wherein a sum of lengths of the one of the first logic cells and the one of the third logic cells is substantially equal to a sum of lengths of the two adjacent second logic cells” in the claim language.
Applicant does not have support in the originally filed specifications for wherein a sum of lengths of the one of the first logic cells and the one of the third logic cells is substantially equal to a sum of lengths of the two adjacent second logic cells.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 12-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 2, 3, 4, 5, 6, and 12, 13, 14, 15, 16, 17, 19, 20. Claim 1 recites the limitation "the first logic cells" in fifth paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination and compact prosecution, examiner shall interpret the first logic cells to be “the plurality of the first logic cells”.
Claims 2-6 are rejected for dependence upon a 112(b) rejected instance claim.
Claims 2-6, 12-17, 19 and 20 are rejected for the same analogous reasons.
Regarding claim 1, 3, 5, and 12, 13, 14, 15, 16, 17, 19, 20. Claim 1 recites the limitation "the second logic cells" in fifth paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim for the same reasons as above.
Claims 2, 3, 5, 12-17, 19 and 20 rejected for the same reasons.
Regarding claims 1, 2, 3, 4, 6, and 12, 13, 19, 20. Claim 1 recites the limitation "the third logic cells" in fifth paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim for the same reasons as above.
Claims 2, 3, 4, 6, 12, 13, 19, and 20 rejected for the same reasons.
Regarding claim 1. Claim 1 recites the limitation “wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells” in the last paragraph of claim 1.
This limitation appears to make the limitation optional as the claims does not require metals lines to be covering the logic cells, nor the metal lines to be inside the logic cells.
The claim requires a plurality of metal lines parallel to each other in a metal layer, and at no point introduced metal lines inside of logic cells.
Claim 2-6 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 15 and 16. Claims 15 and 16 are rejected for the same reasons as claim 1 above
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), Liaw (2018/0005691), and Kim et al (U.S. 2018/0358346)
Regarding claim 1. Kang et al discloses a semiconductor structure, comprising:
a plurality of first logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) having a first cell height (FIG. 1, item H2),
a plurality of second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A) having a second cell height (FIG. 1, item H1), wherein the second cell height (FIG. 1, item H1) is different ([0023]) than the first cell height (FIG. 1, item H2) ;
a plurality of third logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) having the first cell height (FIG. 1, item H2),
a plurality of metal lines (FIG. 2B and 4A, items M1, VDD/VSS) parallel to each other in a metal layer (FIG. 2B and 4A, items M1, VDD/VSS),
wherein the first logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) and the third logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) are arranged in odd rows (FIG. 1, items H2; FIG. 4A) of a cell array (FIG. 1, item 10), and the second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A) are arranged in even rows (FIG. 1, item H1) of the cell array (FIG. 1, item 10),
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first logic cells, each comprising a plurality of multiple-fin transistors
second logic cells, each comprising a plurality of single-fin transistors,
third logic cells, each comprising a plurality of single-fin transistors;
wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.
However, Liaw teaches
first logic cells (FIG. 2, item 122), each comprising a plurality of multiple-fin transistors ([0019], i.e. each of the active regions 124 through 128 in the P-well 122 includes multiple fin active features (also referred to fin active regions)
second logic cells (FIG. 2, item 130), each comprising a plurality of single-fin transistors (([0019], i.e. each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region)),
third logic cells (FIG. 2, item 132), each comprising a plurality of single-fin transistors (([0019], i.e. each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region)),
Since Kang et al and Liaw teach logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al with the teachings of first logic cells, each comprising a plurality of multiple-fin transistors ,second logic cells, each comprising a plurality of single-fin transistors, third logic cells, each comprising a plurality of single-fin transistors as disclosed by Liaw. The use of each of the active regions 124 through 128 in the P-well 122 includes multiple fin active features also referred to fin active regions and each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region in Liaw provides for reducing bit line capacitance and leakage and improved read currents (Liaw, [0021]).
Kang et al and Liaw fails to explicitly disclose
wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.
However, Kim et al teaches wherein the metal lines (FIG. 4, item M11-M13) inside the first (FIG. 4, item STI) and third logic cells (FIG. 4, item AR1) are wider ([0056], i.e. the fifth width W4 of the fourth metal line M14 may be different from the rest) than the metal lines (FIG. 4, item M14) inside the second logic cells (FIG. 4, item AR2).
Since Kang et al, Liaw and Kim et al teach logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al and Liaw with the teachings of wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells as disclosed by Kim et al. The use of the fifth width W4 of the fourth metal line M14 may be different from the rest in Kim et al provides for a semiconductor device structure capable of reducing the level of difficulty of the process for separating a gate contact and a source/drain contact in a cell region defined by a correlation between the width of a cell region, a pitch between metal lines and a width of the metal lines (Kim et al, [0005]).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 2. Kang et al, Liaw, and Kim et al discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kang et al further discloses wherein the second cell height (FIG. 1, item C1-C2 in items H1; FIG. 4A) of the second logic cell (FIG. 1, item C1-C2 in items H1; FIG. 4A) is less ([0023], H2 equal to twice H1) than the first cell height (FIG. 1, item H2) of the first (FIG. 1, item C1-C3 in items H2; FIG. 4A) and third logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A).
Regarding claim 6. Kang et al, Liaw, and Kim et al discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kang et al further discloses wherein a quantity (FIG. 4A, items M1Layer, examiner makes note that there is quantity ten metal lines) of the first group of metal lines (FIG. 4A, items M1 Layer) is greater (FIG. 4A metal lines are greater than FIG. 2B metal lines) than that (FIG. 2B, items M1Layer, examiner makes note that there is quantity six metal lines) of the second group of metal lines (FIG. 2B, items M1 Layer)
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claims 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), Liaw (U.S. 2018/0005691), and Kim et al (U.S. 2019/0358346) as applied to claim 1 above, and further in view of Baek et al (U.S. 2014/0097493)
Regarding claim 3. Kang et al, Liaw, and Kim et al discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kang et al discloses wherein the metal lines (FIG. 2B and 4A, items VDD/VSS) covering the first (FIG. 1, item C1-C3 in items H2; FIG. 4A) and second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A) metal lines (FIG. 2B and 4A, items M1) inside the first (FIG. 1, item C1-C3 in items H2; FIG. 4A) and second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A), and the metal lines (FIG. 2B and 4A, items VDD/VSS) covering the third (FIG. 1, item C1-C3 in items H2; FIG. 4A) and second logic (FIG. 1, item C1-C2 in items H1; FIG. 4A) cells and the metal lines (FIG. 2B and 4A, items M1) inside the second (FIG. 1, item C1-C2 in items H1; FIG. 4A) and third logic (FIG. 1, item C1-C3 in items H2; FIG. 4A) cells.
Kim et al further discloses width ratio of the metal lines (FIG. 4, item M11) inside the first logic cells (FIG. 4, item AR1) to the metal lines (FIG. 4, item M14) inside the second logic cells (FIG. 4, item AR1) is greater than 1.05. ([0056], i.e. and the fifth width W4 of the fourth metal line M14 may be different from the rest)
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II.
Kang et al, Liaw and Kim et al fails to explicitly disclose further discloses wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first and second logic cells, and the metal lines covering the third and second logic cells are wider than the metal lines inside the second and third logic cells.
However Baek et al teaches wherein the metal lines (FIG. 8, item PL1, PL2, PL3) covering the first and second logic cells (FIG. 8, item Ha’) are wider ([0122], i.e. width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6; [0129]) than the metal lines (FIG. 8, item ML1 through ML12) inside the first and second logic cells (FIG. 8, item Ha’), and the metal lines (FIG. 11, item PL1, PL2, PL3) covering the third and second logic cells (FIG. 11, item Hb’) are wider ([0144]-[0148]) than the metal lines (FIG. 11, item ML1 through ML14) inside the second and third logic cells (FIG. 11, item Hb’).
Since Kang et al, Liaw, Kim et al and Baek et al teach logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al, Liaw, and Kim et al with the teachings of wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first and second logic cells, and the metal lines covering the third and second logic cells are wider than the metal lines inside the second and third logic cells as disclosed by Baek et al. The use of width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6 in Baek et al provides for the width of power lines may be adaptively determined according to the height of each of the first and second cells CELLa1 and CELLa2 (Baek et al, [0130]).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II.
Regarding claim 5. Kang et al, Liaw, and Kim et al discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kim et al further discloses width ratio of the metal lines (FIG. 4, item M11) inside the first logic cells (FIG. 4, item AR1) to the metal lines (FIG. 4, item M14) inside the second logic cells (FIG. 4, item AR1) is greater than 1.05. ([0056], i.e. and the fifth width W4 of the fourth metal line M14 may be different from the rest)
Kang et al, Liaw, and Kim et al fails to explicitly disclose further discloses wherein width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2,
However, Baek et al teaches wherein width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2 ([0122], i.e. a width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6)
Since Kang et al, Liaw, Kim et al, and Baek et al teaches logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al, Liaw, and Kim et al with the teachings of the wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells as disclosed by Baek et al. The use of a width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6 in Baek et al provides for semiconductor integrated circuits capable of improving integration by reducing a size of a cell included in a fin field effect transistor (Baek et al, [0006]).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), Liaw (U.S. 2018/0005691), and Kim et al (U.S. 2019/0358346) as applied to claim 1 above, and further in view of Liu (U.S. 2008/0061441)
Regarding claim 4. Kang et al, Liaw, and Kim et al discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kang et al further discloses wherein a plurality of first vias of a via layer under and coupled to the metal lines inside the first logic cells or third logic cell, a plurality of second vias of the via layer under and coupled to the metal lines inside the second logic cells ([0032], i.e. one or more "interconnects" (i.e., conductive elements including (e.g.,) wiring layer pattern(s), contact(s) and/or via(s)) routing common input signal(s)).
Kang et al fails to explicitly disclose wherein a plurality of first vias have larger size than a plurality of second vias.
However, Liu teaches wherein a plurality of first vias have larger size than a plurality of second vias ([0006], i.e. the second via has a second via width greater than the first via width).
Since Kang et al, Liaw, Kim et al, and Liu teaches It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al, Liaw, and Kim et al with the teachings of the wherein a plurality of first vias have larger size than a plurality of second vias as disclosed by Liu et al. The use of the second via has a second via width greater than the first via width in Liu et al provides for improved reliability and lowered cost for achieving the reliability improvement. (Liu et al, [0007]).
Claims 12, 13, 16, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), and Liaw (2018/0005691)
Regarding claim 12. Kang et al discloses a semiconductor structure, comprising:
a plurality of first logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) having a first cell height (FIG. 1, item H2) each comprising a plurality of first fin transistors ([0027]),
a plurality of second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A) having a second cell height (FIG. 1, item H1), each comprising a plurality of second fin transistors ([0027]), wherein the second cell height (FIG. 1, item H1) is different ([0023]) than the first cell height (FIG. 1, item H2) ;
a plurality of third logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) having the first cell height (FIG. 1, item H2) each comprising a plurality of first third fin transistors ([0027]),
wherein the first logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) and the third logic cells (FIG. 1, item C1-C3 in items H2; FIG. 4A) are arranged in odd rows (FIG. 1, items H2; FIG. 4A) of a cell array (FIG. 1, item 10), and the second logic cells (FIG. 1, item C1-C2 in items H1; FIG. 4A) are arranged in even rows (FIG. 1, item H1) of the cell array (FIG. 1, item 10),
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wherein a fin number of each of the first fin transistors in the first logic cells, is greater than a fin number of each of the second fin transistors in the second logic cells and the third fin transistors in the third logic cells
However, Liaw teaches
wherein a fin number ([0019], i.e. each of the active regions 124 through 128 in the P-well 122 includes multiple fin active features (also referred to fin active regions)) of each of the first fin transistors in the first logic cells (FIG. 2, item 122) is greater ([0019]) than a fin number (([0019], i.e. each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region)) of each of the second fin transistors in the second logic cells (FIG. 2, item 130) and the third fin transistors in the third logic cells (FIG. 2, item 132).
Since Kang et al and Liaw teach logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al with the teachings of wherein a fin number of each of the first fin transistors in the first logic cells, is greater than a fin number of each of the second fin transistors in the second logic cells and the third fin transistors in the third logic cells as disclosed by Liaw. The use of each of the active regions 124 through 128 in the P-well 122 includes multiple fin active features also referred to fin active regions and each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region in Liaw provides for reducing bit line capacitance and leakage and improved read currents (Liaw, [0021]).
Regarding claim 13. Kang et al and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 12 above.
Do et al further discloses wherein the first fin transistors comprises a plurality of multiple-fin transistors ([0019], i.e. each of the active regions 124 through 128 in the P-well 122 includes multiple fin active features (also referred to fin active regions)), and the second fin transistors comprises a plurality of single-fin transistors (([0019], i.e. each of the active regions 130 through 132 in the N-well 120 includes a single fin active feature (also referred to fin active region)),
Kang et al further discloses the second cell height of the second logic cell (FIG. 1, item C1-C2 in items H1; FIG. 4A) is less than ([0023]) the first cell height of the first logic cell (FIG. 1, item C1-C3 in items H2; FIG. 4A).
Regarding claim 16. Kang et al and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 12 above.
Kang et al further discloses further comprising: a plurality of metal lines (FIG. 2B and 4A, items M1, VDD/VSS) parallel to each other in a metal layer (FIG. 2B and 4A, items M1, VDD/VSS)
wherein a quantity (FIG. 4A, items M1Layer, examiner makes note that there is quantity ten metal lines) of the first group of metal lines (FIG. 4A, items M1 Layer) is greater (FIG. 4A metal lines are greater than FIG. 2B metal lines) than that (FIG. 2B, items M1Layer, examiner makes note that there is quantity six metal lines) of the second group of metal lines (FIG. 2B, items M1 Layer)
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II.
Regarding claim 19. Kang et al and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 12 above.
Kang et al further discloses wherein one of the first logic cells (FIG. 5B, item F51) is adjacent ([0057]) to one of the third logic cells (FIG. 5B, item F53), and two adjacent second logic cells (FIG. 5B, item F52 and F54) are located adjacent ([0057) to the one of the first logic (FIG. 5B, item F51) cells and the one of the third logic cells (FIG. 5B, item F53).
Regarding claim 20. Kang et al and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 19 above.
Kang et al further discloses wherein a sum of lengths (FIG. 5B, item 1st direction) of the one of the first logic cells (FIG. 5B, item F51) and the one of the third logic (FIG. 5B, item F53) cells is substantially equal (FIG. 5B, shows that the sum of length of F51 and F52 is substantial to the sum of lengths of F52 and F54) to a sum of lengths (FIG. 5B, item 1st direction) of the two adjacent second logic cells (FIG. 5B, item F52 and F54).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), and Liaw (U.S. 2018/0005691) as applied to claim 12 above, and further in view of Liu (U.S. 2008/0061441)
Regarding claim 14. Kang et al, and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 12 above.
Kang et al further discloses wherein a plurality of first vias of a via layer under and coupled to the metal lines inside the first logic cells or third logic cell, a plurality of second vias of the via layer under and coupled to the metal lines inside the second logic cells ([0032], i.e. one or more "interconnects" (i.e., conductive elements including (e.g.,) wiring layer pattern(s), contact(s) and/or via(s)) routing common input signal(s)).
Kang et al fails to explicitly disclose wherein a plurality of first vias have larger size than a plurality of second vias.
However, Liu teaches wherein a plurality of first vias have larger size than a plurality of second vias ([0006], i.e. the second via has a second via width greater than the first via width).
Since Kang et al, Liaw, and Liu teaches logic cells, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed in to modify Kang et al in and Liaw with the teachings of the wherein a plurality of first vias have larger size than a plurality of second vias as disclosed by Liu et al. The use of the second via has a second via width greater than the first via width in Liu et al provides for improved reliability and lowered cost for achieving the reliability improvement. (Liu et al, [0007]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), and Liaw (U.S. 2018/0005691) as applied to claim 12 above, and further in view of Kim et al (U.S. 2019/0358346) and Baek et al (U.S. 2008/0061441)
Regarding claim 15. Kang et al, and Liaw, discloses all the limitations of the semiconductor structure as claimed in claim 1 above.
Kang et al discloses a plurality of metal lines (FIG. 2B and 4A, items M1, VDD/VSS) parallel to each other in a metal layer (FIG. 2B and 4A, items M1, VDD/VSS),
Kang et al, and Liaw fails to explicitly disclose further discloses wherein a width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2, and a width ratio of the metal lines inside the first logic cells to the metal lines inside the second logic cells is greater than 1.05
However, Kim et al teaches wherein a width ratio of the metal lines (FIG. 4, item M11) inside the first logic cells (FIG. 4, item AR1) to the metal lines (FIG. 4, item M14) inside the second logic cells (FIG. 4, item AR1) is greater than 1.05. ([0056], i.e. and the fifth width W4 of the fourth metal line M14 may be different from the rest)
Since Kang et al, Liaw, and Kim et al teach logic cells It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al and Liaw with the teachings of the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells as disclosed by Kim et al. The use of the fifth width W4 of the fourth metal line M14 may be different from the rest in Kim et al provides for a semiconductor device structure capable of reducing the level of difficulty of the process for separating a gate contact and a source/drain contact in a cell region defined by a correlation between the width of a cell region, a pitch between metal lines and a width of the metal lines (Kim et al, [0005].
Kang et al, Liaw, and Kim et al fails to explicitly disclose further discloses wherein width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2,
However, Baek et al teaches wherein width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2 ([0122], i.e. a width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6)
Since Kang et al, Liaw, Kim et al, and Baek et al teaches logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kang et al, Liaw, and Kim et al with the teachings of the wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells as disclosed by Baek et al. The use of a width Wp of each of the first and second power lines PL1 and PL2 may be greater than the width Wm of each of the first through sixth wires ML1 through ML6 in Baek et al provides for semiconductor integrated circuits capable of improving integration by reducing a size of a cell included in a fin field effect transistor (Baek et al, [0006]).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II.
Claims 17, are 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (U.S. 2017/0317100), and Liaw (2018/0005691) as applied to claim 12 above, and further in view of Do et al (U.S. 2016/0056153).
Regarding claim 17. Kang et al and Liaw discloses all the limitations of the semiconductor structure as claimed in claim 12 above.
Kang et al discloses wherein the first logic cells in the same row are isolated from each other ([0045], i.e. the standard cells may be insulated from one another) and the second logic cells in the same row are isolated from each other ([0045], i.e. the standard cells may be insulated from one another).
Kang et al fails to explicitly disclose are isolated by a dielectric material.
However, Do et al teaches wherein the first logic cells in the same row are isolated from each other ([0056], i.e. Each of the logic cells C1, C2, C3, and C4 may include active regions that are isolated from each other by a device isolation layer ST) by a dielectric material ([0059], i.e. The device isolation layer ST may include, for example, a silicon oxide layer), and the second logic cells in the same row are isolated from each other ([0056], i.e. Each of the logic cells C1, C2, C3, and C4 may include active regions that are isolated from each other by a device isolation layer ST) by the dielectric material ([0059], i.e. The device isolation layer ST may include, for example, a silicon oxide layer).
Since Kang et al, Liaw and Do et al teach logic cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structures as disclosed to modify Kang et al and Liaw with the teachings of are isolated by a dielectric material as disclosed by Do et al. The use of the device isolation layer may include, for example, a silicon oxide layer in Do et al provides for active regions that are isolated from each other by a device isolation layer (Do et al, [0056]).
Regarding claim 18. Kang et al, Liaw, and Do et al discloses all the limitations of the semiconductor structure as claimed in claim 17 above.
Do et al further discloses wherein the dielectric material comprises a plurality of segments (FIG. 3A and 3B, items ST1, ST2, ST3) parallel to each other ([0059]-0062]).
Conclusion
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815