DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 06/25/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,7-9,11,21,23-24 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0207397 A1 to GARDNER et al., “Gardner”, in view of US 2024/0379679 A1 to Li et al., “Li”.
Regarding claim 1, Gardner discloses a semiconductor structure (e.g. FIG. 1A), comprising:
a first transistor (110, ¶ [0057]), wherein the first transistor comprises:
a first channel layer (115, ¶ [0057]); and
a first gate structure (114, “gate-all-around (GAA)” ¶ [0057]) wrapping around the first channel layer (115);
a second transistor (120, ¶ [0057]), wherein the second transistor comprises:
a second channel layer (125, ¶ [0057]); and
a second gate structure (124, ¶ [0057]) wrapping around the second channel layer (125);
a bonding structure (130, ¶ [0058]) vertically sandwiched between the first transistor (110) and the second transistor (120), wherein the bonding structure comprises:
a first dielectric bonding layer (131, ¶ [0058]-[0059]) attached to the first gate structure (114);
a second dielectric bonding layer (133, ¶ [0058]-[0059]) attached to the first dielectric bonding layer (131) and the second gate structure (124).
Although Gardner teaches (e.g. FIG. 18) a conductive structure (357, ¶ [0093]) connecting the first gate structure to the second gate structure, Gardner fails to clearly teach a first conductive bonding structure formed through the first dielectric bonding layer and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.
Li teaches (e.g. FIG. 5) wherein a single dielectric bonding layer (124) includes a single conductive bonding structure (506A or 506B, ¶ [0054],[0055]).
It would have been obvious to one having ordinary skill in the art to have formed the device of Gardner with each of the first and second dielectric bonding layers of Garnder including a conductive bonding as taught by Li (such that the combination yields first and second conductive bonding structures) in order to desirably interconnect the transistors using reduced area (Li ¶ [0054], since the contacts 506A/506B of Li take up less area than Gardner’s FIG. 18 conductive structure 357).
Regarding claim 2, Gardner in view of Li yields the semiconductor structure as claimed in claim 1, and Gardner further discloses first source/drain structures (112, ¶ [0057]) attached to opposite sides of the first channel layer (115); and second source/drain structures (122, ¶ [0057]) attached to opposite sides of the second channel layer (125), wherein the first dielectric bonding layer (131) laterally extends from a top surface of the first gate structure (114) to vertically overlap the first source/drain structures (112).
Regarding claim 7, Gardner discloses a semiconductor structure (e.g. FIG. 1A), comprising:
a p-type transistor (120, ¶ [0062]), wherein the p-type transistor comprises:
a first channel layer (125, ¶ [0057]);
a first source/drain structure (122, ¶ [0057]) and a second source/drain structure (other 122) attached to opposite sides of the first channel layer in a first direction (x-direction); and
a first gate structure (124, ¶ [0057]) wrapping around the first channel layer (125) and extending in a second direction (e.g. y direction);
a first conductive structure (FIG 18 conductive structure 357, ¶ [0093]) connected to the p-type transistor and extending in a third direction (z direction);
an n-type transistor (110, ¶ [0057]) connected to the conductive bonding structure (357), wherein the n-type transistor comprises:
a second channel layer (115, ¶ [0057]);
a third source/drain structure (112, ¶ [0057]) and a fourth source/drain structure (other 112) attached to opposite sides of the second channel layer (115); and
a second gate structure (114, “gate-all-around (GAA)” ¶ [0057]) wrapping around the second channel layer.
Gardner fails to clearly teach wherein the first conductive structure (357) is bonded to the p-type transistor, and a second conductive bonding structure bonded to the first conductive bonding structure in a third direction, the second conductive bonding structure bonded to the n-type transistor.
Li teaches (e.g. FIG. 5) wherein a single dielectric bonding layer (124) includes a single conductive bonding structure (506A or 506B, ¶ [0054],[0055]).
It would have been obvious to one having ordinary skill in the art to have formed the device of Gardner with each of the first and second dielectric bonding layers of Garnder including a conductive bonding as taught by Li (such that the combination yields first and second conductive bonding structures) in order to desirably interconnect the transistors using reduced area (Li ¶ [0054], since the contacts 506A/506B of Li take up less area than Gardner’s FIG. 18 conductive structure 357).
Regarding claim 8, Gardner in view of Li yields the semiconductor structure as claimed in claim 7, and Gardner further discloses a first dielectric bonding layer (133) bonded to the p-type transistor (120) in the third direction; and a second dielectric bonding layer (131) bonded to the first dielectric bonding layer (133) and the n-type transistor (110), and Gardner as modified by Li further yields wherein the first conductive bonding structure (Li one of 506A/506B in each bonding layer 124) is formed through the first dielectric bonding layer (Gardner layer 133), and the second conductive bonding structure (Li one of 506A/506B in each bonding layer 124) is formed through the second dielectric bonding layer (Gardner layer 131).
Regarding claim 9, Gardner in view of Li yields the semiconductor structure as claimed in claim 8, and Gardner further teaches wherein a closest distance between the first gate structure (124) and the second gate structure (114) is substantially equal to a sum of a thickness of the first dielectric bonding layer (133) and a thickness of the second dielectric bonding layer (131) in the third direction (z direction).
Regarding claim 11, Gardner in view of Li yields the semiconductor structure as claimed in claim 7, and Gardner as modified by Li further yields wherein the first conductive bonding structure (Li one of 506A/506B in each bonding layer 124 formed through Gardner’s layer 133) is in contact with the first gate structure (124), and the second conductive bonding structure (Li one of 506A/506B in each bonding layer 124 formed through Gardner’s layer 131) is in contact with the second gate structure (114) in the third direction (z direction).
Regarding claim 21, Gardner discloses a semiconductor structure (e.g. FIG. 1A), comprising:
a first transistor (110, ¶ [0057]), wherein the first transistor comprises:
first channel layers (115, ¶ [0057]);
first source/drain structures (112, ¶ [0057]) attached to the first channel layers in a first direction; and
a first gate structure (114, “gate-all-around (GAA)” ¶ [0057]) wrapping around the first channel layers (115);
a first dielectric bonding layer (131, ¶ [0058]-[0059]) formed over the first gate structure;
a second dielectric bonding layer (133, ¶ [0058]-[0059]) attached to the first dielectric bonding layer (131);
a second transistor (120, ¶ [0057]) vertically stacked over the second dielectric bonding layer (133), wherein the second transistor comprises:
second channel layers (125, ¶ [0057]);
second source/drain structures (122, ¶ [0057]) attached to the second channel layers (125) in the first direction (x direction); and
a second gate structure (124, ¶ [0057]) wrapping around the second channel layers,
wherein (FIG. 18) a conductive bonding structure (357, ¶ [0093]) is electrically connected to the first transistor (110), and the conductive bonding structure (357) is electrically connected to the second transistor (120).
Gardner fails to clearly teach a first conductive bonding structure formed through the first dielectric bonding layer and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.
Li teaches (e.g. FIG. 5) wherein a single dielectric bonding layer (124) includes a single conductive bonding structure (506A or 506B, ¶ [0054],[0055]).
It would have been obvious to one having ordinary skill in the art to have formed the device of Gardner with each of the first and second dielectric bonding layers of Garnder including a conductive bonding as taught by Li (such that the combination yields first and second conductive bonding structures) in order to desirably interconnect the transistors using reduced area (Li ¶ [0054], since the contacts 506A/506B of Li take up less area than Gardner’s FIG. 18 conductive structure 357).
Regarding claim 23, Gardner in view of Li yields the semiconductor structure as claimed in claim 21, and Gardner as modified by Li yields wherein the first conductive bonding structure (Li one of 506A/506B in each bonding layer 124 formed through Gardner’s layer 131) is connected to the first gate structure, and the second conductive bonding structure (Li one of 506A/506B in each bonding layer 124 formed through Gardner’s layer 133) is connected to the second gate structure.
Regarding claim 24, Gardner in view of Li yields the semiconductor structure as claimed in claim 21, and Li further teaches (e.g. FIG. 5) wherein a width of the first conductive bonding structure (506A or 506B) is smaller than a width of the first gate structure (one of gates 112A or 130A) in the first direction (x direction).
Allowable Subject Matter
Claims 3-6,10,12-16,22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Gardner teaches a bonding transistors with first and second dielectric layers as discussed above and prior art e.g. US 2024/0021586 A1 to Li et al. teaches (FIG. 1) bonding transistors and forming gate-to-gate bonding structures (VIA(5)) and source/drain bonding structures (VIA(1), VIA(6)). Prior art e.g. Li teaches forming conductive bonding structures through dielectric bonding layer as discussed above.
However, prior art fails to reasonably teach or suggest a first backside via connected to a first one of the first source/drain structures, wherein the first backside via and the first conductive bonding structure are located at opposite sides of the first transistor as claimed in claim 3 together with all of the limitations of claims 1 and 2. Claims 4-6 are objected to as allowable insofar as they depend upon and inherit all of the limitations of claim 3.
Additionally, prior art fails to reasonably teach or suggest wherein the first conductive bonding structure is spaced apart from the second source/drain structure in the first direction or in the second direction but is electrically connected to the second source/drain structure as claimed in claim 10 together with all of the limitations of claim 7. Similarly, prior art fails to reasonably teach or suggest a third conductive bonding structure electrically connected to the first source/drain structure; and a fourth conductive bonding structure bonded to the third conductive bonding structure in the third direction and electrically connected to the third source/drain structure, wherein a thickness of the third conductive bonding structure in the third direction is greater than a thickness of the first conductive bonding structure in the third direction as claimed in claim 12 together with all of the limitations of claim 11. Furthermore, prior art fails to reasonably teach or suggest wherein the first conductive bonding structure is in contact with the first source/drain structure in the third direction as claimed in claim 13 together with all of the limitations of claim 7. Furthermore, prior art fails to reasonably teach or suggest wherein the first conductive bonding structure comprises: a first conductive via; and a first bonding pad formed over the first conductive via, wherein the first conductive via and the first bonding pad are made of different conductive materials as claimed in claim 14 together with all of the limitations of claim 7. Furthermore, prior art fails to reasonably teach or suggest a first backside conductive via electrically connected to the p-type transistor; and a first interconnect structure attached to the first backside conductive via, wherein the first interconnect structure and the n-type transistor are at opposite sides of the p-type transistor in the third direction, as claimed in claim 15 together with all of the limitations of claim 7. Claim 16 is objected to as allowable insofar as it depends upon and inherits all of the limitations of claim 15.
Lastly, prior art fails to reasonably teach or suggest wherein the first conductive bonding structure is electrically connected to the first source/drain structures as claimed in claim 22 together with all of the limitations of claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0260971 A1 to Mochizuki et al. teaches (FIG. 3) a conductive structure (162 and 262, ¶ [0061],[0083],[0086]) including a first conductive bonding structure (162) formed through a first dielectric bonding layer (160) and a second conductive bonding structure (262) formed through a second dielectric bonding layer (260) and bonded to the first conductive bonding structure (162).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Eric A. Ward/Primary Examiner, Art Unit 2891
Prosecution Insights