DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figs. 3-4) in the reply filed on 7.20.2026 is acknowledged. Claims 1-10, 12-13 and 15-20 are elected.
Claims 11 and 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7.20.2026.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 12-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Houle et al. (US 20040262743 A1).
Regarding claim 1, Houle discloses (Fig. 2A) an electronic device, comprising:
a printed circuit board (220);
an integrated circuit (210) that is coupled to the printed circuit board on a first side (bottom of 210) and a thermal solution (230 and/or 250) on a second side (top of 210);
a thermal interface material (240) that is disposed between the integrated circuit and the thermal solution; and
a first barrier seal (unlabeled, underfill material shown around 212 in Fig. 2A) that is disposed around a perimeter of the integrated circuit and is (inherent, otherwise shorting of 212 would be present) electrically insulative (Fig. 2A).
In case “substrate 220, such as a circuit board” is not a “printed” circuit board as claimed, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a PCB because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
In addition, in case the first barrier seal of the prior art is not “electrically insulative” as claimed, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include an electrically insulative material as claimed so as to prevent shorting of solder balls which are surrounded by said first barrier seal.
Regarding claim 5, Houle discloses the electronic device of claim 1, further comprising a second barrier seal (234) that is disposed around the perimeter of the integrated circuit (Figs. 2A-2B) and forms a seal between a (bottom) surface of the thermal solution (as 230) and a (at 220) surface of an integrated-circuit package (220+210) that includes the integrated circuit (Figs. 2A-2B).
Regarding claim 6, Houle discloses the electronic device of claim 5, wherein the second barrier seal (234) fills an air gap that is located between the (bottom) surface of the thermal solution and the (at 220) surface of the integrated-circuit package (Figs. 2A-2B, 234 occupies a space therefore fills and air gap).
Regarding claim 7, Houle discloses the electronic device of claim 5, wherein the second barrier seal (234) is disposed continuously around the perimeter of the integrated circuit (Fig. 2B, [0023] – “sealant 234 is further included to isolate and secure the integrated heat spreader 230 to the substrate 220”).
Regarding claim 12, Houle discloses the electronic device of claim 1, wherein the thermal solution (230 and/or 250) includes at least one of a heatsink (“integrated heat spreader 230” and “heat sink 250”), a vapor chamber, or a liquid cold plate.
Regarding claim 13, Houle discloses the electronic device of claim 1, wherein the first barrier seal (unlabeled, underfill material shown around 212 in Fig. 2A) does not (directly physically) contact the thermal solution (230 and/or 250).
Regarding claim 20, Houle discloses (Figs 1-2B) computing system (1), comprising:
a memory (10 or parts thereof); and
an electronic device (200) that includes:
a printed circuit board (220);
an integrated circuit (210) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (230) on a second side (top);
a thermal interface material (240) that is disposed between the integrated circuit and the thermal solution; and
a first barrier seal (unlabeled, underfill material shown around 212 in Fig. 2A) that is disposed around a perimeter of the integrated circuit and is (inherent, otherwise shorting of 212 would be present) electrically insulative (Fig. 2A).
In case “substrate 220, such as a circuit board” is not a “printed” circuit board as claimed, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a PCB because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
In addition, in case the first barrier seal of the prior art is not “electrically insulative” as claimed, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include an electrically insulative material as claimed so as to prevent shorting of solder balls which are surrounded by said first barrier seal.
Claims 1, 5-8, 10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Edwards et al. (US 20110042784 A1).
Regarding claim 1, Edwards discloses an electronic device, comprising:
a printed circuit board (not shown, below 131, [0024], Fig. 1);
an integrated circuit (120) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (110) on a second side (bottom);
a thermal interface material (150) that is disposed between the integrated circuit and the thermal solution; and
a first barrier seal (140 or 170) that is disposed around a perimeter of the integrated circuit (Figs. 1 and 2) and is electrically insulative ([0034] or [0023]).
Regarding claim 5, Edwards discloses the electronic device of claim 1, further comprising a second barrier seal (as 140 and 170 being the first barrier seal) that is disposed around the perimeter of the integrated circuit (120) and forms a seal between a surface of the thermal solution (“the cap 110 may instead be coupled with the barrier element 140”, [0021]) and a surface (at 130) of an integrated-circuit package (130+120) that includes the integrated circuit (Fig. 1).
Regarding claim 6, Edwards discloses the electronic device of claim 5, wherein the second barrier seal (140) fills an air gap that is located between the surface of the thermal solution and the surface of the integrated-circuit package (Fig. 1, 140 occupies a space therefore fills and air gap).
Regarding claim 7, Edwards discloses the electronic device of claim 5, wherein the second barrier (140) seal is disposed continuously around the perimeter of the integrated circuit (Figs. 1-2).
Regarding claim 8, Edwards discloses the electronic device of claim 5, wherein the surface (at 130) of the integrated-circuit package (130+120) comprises either a surface of a stiffener included in the integrated-circuit package or a (top) surface of a packaging substrate (140) included in the integrated-circuit package (Fig. 1).
Regarding claim 10, , Edwards discloses the electronic device of claim 5, wherein the second barrier seal (140) comprises one of an elastic material (“a plastic” which exhibits even a minimal level of elasticity) or a hot melt adhesive.
Regarding claim 12, Edwards discloses the electronic device of claim 1, wherein the thermal solution (110) includes at least one of a heatsink ([0019]), a vapor chamber, or a liquid cold plate.
Regarding claim 13, Edwards discloses the electronic device of claim 1, wherein the first barrier seal (140 or 170) does not contact the thermal solution (110, Fig. 1).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Edwards et al. (US 20110042784 A1).
Regarding claim 20, Edwards discloses a computing system, comprising:
an electronic device that includes:
a printed circuit board (not shown, below 131, [0024], Fig. 1);
an integrated circuit (120) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (110) on a second side;
a thermal interface material (150) that is disposed between the integrated circuit and the thermal solution; and
a first barrier seal (140 or 170) that is disposed around a perimeter of the integrated circuit and is electrically insulative ([0034] or [0023]).
Edwards fails to disclose a memory in addition to the electronic device.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a memory as claimed in the system of Edwards so as to integrate devices with different functionalities into a system and/or because the use of conventional materials (a memory in this case) to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 1-7, 10, 12-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dhane et al. (US 20200203254 A1).
Regarding claim 1, Dhane discloses an electronic device, comprising:
a printed circuit board (602, Fig. 6);
an integrated circuit (e.g., 604) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (IHS) on a second side (top, Figs. 1-4);
a thermal interface material (128/328) that is disposed between the integrated circuit (108/112/308) and the thermal solution (IHS); and
a first barrier seal (110/310 or 114/314) that is disposed around a perimeter of the integrated circuit and is electrically insulative (Figs. 1-4).
Regarding claim 2, Dhane discloses the electronic device of claim 1, wherein the integrated circuit (108, Fig. 1) is mounted on a packaging substrate (104), and the first barrier seal (as 114) is positioned to (at least indirectly) prevent one or more electrically conductive constituents ([0031-0032]) included in the thermal interface material (as 128) from contacting one or more electronic components (other 108, [0019] – “The substrate 104 can include a number of integrated circuits thereon in the form of one or more die 108”) that also are mounted on the packaging substrate (Fig. 1, [0019] and [0031]).
Regarding claim 3, Dhane discloses the electronic device of claim 2, wherein the first barrier seal (as 114) is disposed (indirectly on) on the one or more electronic components (other 108 per [0019]).
Regarding claim 4, Dhane discloses the electronic device of claim 1, wherein the first barrier seal (as 114) is positioned to (at least indirectly) prevent one or more electrically conductive constituents ([0031-0032]) included in the thermal interface material (128) from contacting one or more electronic components (e.g., 606) that are mounted on the printed circuit board (602, Figs. 1 and 6).
Regarding claim 5, Dhane discloses the electronic device of claim 1, further comprising a second barrier seal (as 114/314 and the first barrier seal as 110/310) that is disposed around the perimeter of the integrated circuit (108/308) and forms a seal between a surface of the thermal solution (IHS) and a surface (at 110/310) of an integrated-circuit package that includes the integrated circuit (Figs. 1-4).
Regarding claim 6, Dhane discloses the electronic device of claim 5, wherein the second barrier (114/314) seal fills an air gap (a space) that is located between the surface of the thermal solution (IHS) and the surface of the integrated-circuit package (Figs. 1-4).
Regarding claim 7, Dhane discloses the electronic device of claim 5, wherein the second barrier seal (as 114/314) is disposed continuously around the perimeter of the integrated circuit (Fig. 2).
Regarding claim 10, Dhane discloses the electronic device of claim 5, wherein the second barrier seal (114/314) comprises one of an elastic material ([0023]; a degree, even if minimal, of elasticity is included therein) or a hot melt adhesive (“layer 114 in some examples is formed from the same material as the polymer layer 110” – [0026]).
Regarding claim 12, Dhane discloses the electronic device of claim 1, wherein the thermal solution (IHS) includes at least one of a heatsink (Figs. 1-3), a vapor chamber, or a liquid cold plate.
Regarding claim 13, Dhane discloses the electronic device of claim 1, wherein the first barrier seal (as 110) does not contact the thermal solution (IHS, Fig. 1).
Regarding claim 20, Dhane discloses the a computing system (Fig. 6), comprising:
a memory (e.g., DRAM); and
an electronic device that includes:
a printed circuit board (602);
an integrated circuit (604) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (IHS) on a second side (Figs. 1-4);
a thermal interface material (128/328) that is disposed between the integrated circuit (108/112/308) and the thermal solution (IHS); and
a first barrier seal (110/310 or 114/314) that is disposed around a perimeter of the integrated circuit and is electrically insulative (Figs. 1-4).
Claims 9 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Dhane et al. (US 20200203254 A1).
Regarding claim 9, Dhane fails to disclose the electronic device of claim 5, wherein the second barrier seal (as 114/314) has a softening temperature that is less than or equal to an operating temperature of the integrated circuit.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure the second barrier seal (as 114/314) has a softening temperature that is less than or equal to an operating temperature of the integrated circuit as claimed in the device of Dhane so as to allow for minor physical deformation during temperature cycling and prevent damage to packaged devices while still preventing leaks from the liquid TIM.
Regarding claim 15, Dhane discloses an electronic device, comprising:
a printed circuit board (602, Fig. 6);
an integrated circuit (e.g., 604) that is coupled to the printed circuit board on a first side (bottom) and a thermal solution (IHS) on a second side (top, Figs. 1-4);
a thermal interface material (128/328) that is disposed between the integrated circuit and the thermal solution (Figs. 1-4); and
a first barrier seal (114/314) that is disposed around a perimeter of the integrated circuit (Figs. 1-4)
Dhane fails to disclose the first barrier seal has a softening temperature that is less than or equal to an operating temperature of the integrated circuit.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure the first barrier seal (114/314) has a softening temperature that is less than or equal to an operating temperature of the integrated circuit as claimed in the device of Dhane so as to allow for minor physical deformation during temperature cycling and prevent damage to packaged devices while still preventing leaks from the liquid TIM.
Regarding claim 16, Dhane discloses the electronic device of claim 15, wherein the first barrier seal (114/314) comprises a seal between a surface of the thermal solution (IHS) and a surface (at 110/310) of an integrated-circuit package that includes the integrated circuit (Figs. 1-4).
Regarding claim 17, Dhane discloses the electronic device of claim 15, further comprising a second barrier seal (110/310) that is disposed around a perimeter of the integrated circuit and is electrically insulative (Figs. 1-4).
Regarding claim 18, Dhane discloses the electronic device of claim 17, further comprising one or more electronic components (more than one 108, [0019]) mounted on a packaging substrate (104/304), wherein the integrated circuit (108) is mounted on the packaging substrate and wherein the second barrier seal (110/310) is positioned to prevent (due to 111/311 and prevent at least indirectly) one or more electrically conductive constituents ([0031]) included in the thermal interface material from contacting the one or more electronic components.
Regarding claim 19, Dhane discloses the electronic device of claim 17, further comprising one or more electronic components (more than one 108, [0019]) mounted on a packaging substrate (104/304), wherein the integrated circuit (108) is mounted on the packaging substrate and wherein the second barrier seal (110/310) is disposed on (indirectly) the one or more electronic components (other 108) mounted on the packaging substrate (Figs. 1-4, [0022] – “polymer layer 110 that is coplanar (or slightly higher) than the second surface of the die 108”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20210327782 A1 to Han et al. discloses a barrier (104) surrounding a TIM (108, Figs. 1-2).
US 20220262759 A1 to Tuschida et al. discloses a seal member (33) surrounding a TIM (31) and a chip (11, Fig. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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