Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment
The amendment filed on 12/05/2025 has been entered into this application. Claims 5 and 7 are cancelled.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-13 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, the claimed invention is directed to a method comprising an abstract idea without significantly more. The claim(s) recite(s) “A test method for a wafer, comprising: acquiring data of an optical characteristic of a test key of the wafer (i.e. wherein the test key comprises a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas) using an optical scatterometer” “comparing the data with corresponding data of a standard sample without a crack and obtaining a difference between the data and the corresponding data” and “determining that a crack is formed in the test key and a crack condition in the chip areas does not meet a criterion of the wafer when the difference is larger than a tolerance; and determining that the crack condition in the chip areas meets the criterion of the wafer when the difference is smaller than or equal to the tolerance”. The limitations in the claim are directed to a program for acquiring optical data of a wafer and comparing it to data of a standard wafer to determine if there is any damage. The claim recites the judicial exception of an abstract idea of finding differences which falls within the category of mathematical concepts/mental processes (See MPEP 2106.04(a)(2)). The “mathematical concepts” abstract idea grouping is defined as mathematical relationships, mathematical formulas or equations, mathematical calculations. The claim limitations are considered mathematical concepts because they correspond to a mathematical relationship and performing a mathematical calculation. The "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions.
The claim limitations are considered mental processes because they correspond to a determination of whether a crack exists based on comparison, which is a step that could be performed in the human mind.
This judicial exception is not integrated into a practical application because the claims only include an “optical scatterometer” and does not tie the abstract idea to a practical application. The use of an “optical scatterometer” is well-understood, routine, and conventional in the art (e.g. Phan US 6818360 B1). As noted above, the claims recite data gathering as “acquiring data of an optical characteristic” and “comparing the data with corresponding data of a standard sample without a crack and obtaining a difference between the data and the corresponding data”, and “determining that a crack is formed in the test key and a crack condition in the chip areas does not meet a criterion of the wafer when the difference is larger than a tolerance” and “determining that the crack condition in the chip areas meets the criterion of the wafer when the difference is smaller than or equal to the tolerance”, which appear to all be mathematical calculations.
While an optical scatterometer is generally claimed, it is noted that Gottschalk v. Benson ‘‘held that simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle’. Further, the claims only generally link the use of the judicial exception into the particular technological environment defect detection in wafers. The high generality of this technological environment amounts to merely indicating a field of use or technological environment in which to apply a judicial exception and does not amount to significantly more than the exception itself, and thus does not integrate the judicial exception into a practical application.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because these are well-understood, conventional activities previously known to the industry, recited at a high level of generality. The recitation of the limitations amounts to mere instructions to implement the abstract idea on a computer. As such, there is no inventive concept sufficient to transform the claimed subject matter into a patent-eligible application. The claim does not amount to significantly more than the abstract idea itself.
Therefore, claim 1 is ineligible.
Claims 2-5 recite mere routine data gathering which is insignificant extra-solution activity per MPEP 2106.05(g)) and do not offer a meaningful limitation. The claims recite generic components configured to implement the same judicial exception as in claim 1. The claims do not amount to significantly more than the underlying mental process for the same reasons as applied above in claim 1.
Claims 6-13 depend from claim 1 and are rejected for the same reasons as claim 1 as the claims recite a judicial exception which is not integrated into a practical application nor provide an inventive concept.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 6818360 B1 (Phan, previously cited reference) in light of US 20090108258 A1 (An, previously cited reference), and further in view of Pittner (US 20200051875 A1, previously cited reference).
As to claim 1, Phan teaches a test method for a wafer (Col. 3, lines 32-39), comprising:
acquiring data of an optical characteristic of a test key of the wafer using an optical scatterometer (Abstract, Fig. 12 shows step 1206 measure via scatterometry), wherein the optical characteristic is variation of reflectivity with wavelength (Fig. 16, Fig. 19, Col. 18 lines 57-65 teach reflectivity),
comparing the data with corresponding data of a standard sample without a crack and obtaining a difference between the data and the corresponding date (Col. 3 lines 60-65, teach comparison to desired signatures, Fig. 12 step 1210)
determining that a crack is formed in the test key and a crack condition in the chip areas does not meet a criterion of the wafer when the difference is larger than a tolerance (Col. 15, lines 52-64, Fig. 11);
and determining that the crack condition in the chip areas meets the criterion of the wafer when the difference is smaller than or equal to the tolerance (Col. 15, lines 52-55 teach acceptable values, Fig. 11 Col. 17, lines 4-7 teach threshold).
Phan is silent to: wherein the wafer having chip areas and a frame area surrounding and separating the chip areas, and the test key is disposed in the frame area.
However, An from the same field of endeavor teaches of a wafer (200, Fig. 6) having chip areas (Fig. 6, [0042]) and a frame area (passivation layer 230) surrounding and separating the chip areas (Fig. 6, [0042]), and the test key is disposed in the frame area (240 conductive layers).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to include the wafer design of An in order to yield the predictable result of having a better performing semiconductor device (Abstract of An). Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Phan wafer by substitution, substituting Phan wafer with An wafer design, since the propose modification by substitution of wafer of the prior art An would not change the principle of operation of the prior art Phan invention being modified.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Phan in the manner set forth in applicant’s claim, in view of the teaching of An in order to improve and enhance semiconductor/wafer fabrication, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954).
Further, Phan when modified by An, Phan teaches of wherein the test key comprises a plurality of test fin features arranged in parallel (wafer having chip areas and a frame area surrounding and separating the chip areas, and the test key is disposed in the frame area is being interpreted as “test fin features”), the test fin features having a space equal to a minimum space in the chip areas (Phan, Fig. 6 shows test fins equally spaced apart, i.e. having some “minimum space”).
Still lacking, Phan when modified by An fail to explicitly specify a pitch equal to a minimum pitch in the chip areas.
Pittner from the same field of endeavor teaches of a semiconductor structure having predetermined pitch (Abstract)[0006][0117].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Phan when modified by An in view of Pittner to have a pitch equal to a minimum pitch in the chip areas as suggested by Pittner in order to yield the predictable result of being able to use a probe card to test the functionality of the chips easily and with good quality ([0116-117] of Pittner), and in order to improve and enhance semiconductor/wafer fabrication, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Phan when modified by An in the manner set forth in applicant’s claim, in view of the teaching of Pittner in order to yield the predictable result of being able to use a probe card to test the functionality of the chips easily and with good quality ([0116-117] of Pittner), and in order to improve and enhance semiconductor/wafer fabrication, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954).
As to claim 2, the combination teaches the test method according to claim 1.
Phan teaches: wherein acquiring the data of the optical characteristic of the test key of the wafer using the optical scatterometer is conducted before all manufacturing processes of the wafer are completely completed (Col. 16 lines 40-50 teach checking for defects and if none are found processing is continued, i.e. before all manufacturing processes of the wafer are completely completed).
As to claim 3, the combination teaches the test method according to claim 1.
Phan teaches: wherein acquiring the data of the optical characteristic of the test key of the wafer using the optical scatterometer (Fig. 12, step 1206) comprises:
directing light beams incident from the optical scatterometer to the test key (light from laser 1302, to sample 1304, Fig. 13); and
collecting light beams reflected from and/or transmitting through the test key to the optical scatterometer (photodetector 1308 detects light reflected from sample, 1306, Col. 17, lines 22-30).
As to claim 4, the combination teaches the test method according to claim 3.
Phan teaches: wherein acquiring the data of the optical characteristic of the test key of the wafer using the optical scatterometer further comprises:
analyzing the light beams reflected from and/or transmitting through the test key to the optical scatterometer (Fig. 13, Col. 17 lines 30-35 teach microprocessor 1310 is used to process readouts).
As to claim 6, the combination teaches the test method according to claim 1.
Phan teaches: wherein the data is plotted as a reflectivity-wavelength graph (Fig. 19, Col. 18 lines 37-40).
As to claim 8, the combination teaches the test method according to claim 1.
Phan teaches: wherein the difference is a value of difference values at a plurality of wavelengths or incidence angles (Col. 6 lines 27-36).
Phan is silent to: wherein the difference is an average value.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to try making the difference being an average value in order to yield the predictable result of obtaining one value which makes it easier and quicker for the comparison to be calculated.
As to claim 12, the combination teaches the test method according to claim 1.
Phan teaches: wherein when the difference is smaller than or equal to the tolerance, it is determined that the crack condition in the chip areas meets the criterion of the wafer, and a profile parameter of the test key is reported (Col. 11 lines 37-42).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over US US 6818360 B1 (Phan, previously cited reference) in light of US 20090108258 A1 (An, previously cited reference), and further in view of Pittner (US 20200051875 A1, previously cited reference), and in light of US 20200175664 A1 (Konecky, previously cited reference).
As to claim 9, the combination teaches the test method according to claim 1.
The combination is silent to: wherein the tolerance is determined according to a value of goodness of fit.
However, Konecky teaches a semiconductor defect inspection method (Abstract) wherein the tolerance is determined according to a value of goodness of fit ([0035] teaches goodness of fit to establish threshold).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to include determining the tolerance is determined according to a value of goodness of fit as suggested by Konecky in order to yield the predictable result of creating a reliable analysis of defect identification.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6818360 B1 (Phan, previously cited reference) in light of US 20090108258 A1 (An, previously cited reference), and further in view of Pittner (US 20200051875 A1, previously cited reference), and in light of CN117710289A (Zheng, previously cited reference) (English machine translation submitted herewith).
As to claim 10, the combination teaches the test method according to claim 1, wherein when the difference is larger than the tolerance, it is determined that a crack is formed in the test key and the crack condition in the chip areas does not meet the criterion of the wafer.
Phan is silent to: an alarm is given.
However, Zheng teaches a method and system for detecting wafer defects with an alarm system (Abstract).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to include the alarm system of Zheng in order to yield the predictable result of notifying a user so that they can take appropriate corrective action.
As to claim 11, the combination teaches the test method according to claim 10.
Phan is silent to: wherein the alarm is given by a warning window.
However, Zheng teaches wherein the alarm is given by a warning window ([0126] teaches the defect information is displayed and transmitted to the alarm system).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to have the alarm be given by a warning as suggested by Zheng, in order to yield the predictable result of showing the user the defect information so that appropriate corrective action can be taken.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over US US 6818360 B1 (Phan, previously cited reference) in light of US 20090108258 A1 (An, previously cited reference), and further in view of Pittner (US 20200051875 A1, previously cited reference), and in light of US 20120322170 A1 (Chou, previously cited reference).
As to claim 13, the combination teaches the test method according to claim 1.
Phan teaches: further comprising: forming the standard sample having a configuration substantially same as a configuration of the test key (Abstract teaches monitoring samples during fabrication process i.e. more than one sample is monitored and generating feedback/feedforward control data, i.e. each sample is used as a “test key” as information is gained and updated from each sample, checking for defects).
The combination is silent to: and confirming that no crack is formed in the standard sample using at least one of SEM or FIB.
However, Chou teaches a fault detecting method of a semiconductor device [0001] comprising confirming that no crack is formed in the standard sample using at least one of SEM or FIB ([0009] teaches SEM).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to include confirming that no crack is formed in the standard sample using at least one of SEM or FIB to yield the predictable result of inspecting morphology/topology of a sample ([0009] of Chou), further confirming the sample is not defective in addition to the scatterometry inspection.
Claim(s) 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20090108258 A1 (An, previously cited reference) in light of US 20200051875 A1 (Pittner, previously cited reference).
As to claim 14, An teaches a wafer (200, Fig. 6), having chip areas (Fig. 6, [0042]) and
a frame area (passivation layer 230 and dielectric layer 220) surrounding and separating the chip areas (Fig. 6, [0038] teaches separation by passivation layer),
the wafer comprising: a test key disposed in the frame area (multiple of 240 forming test key), the test key comprising a plurality of test fin features arranged in parallel (240, Fig. 6),
the test fin features having a space equal to a minimum space in the chip areas (Fig. 6 shows test fins equally spaced apart, i.e. having some “minimum space”).
The combination is silent to: a pitch equal to a minimum pitch in the chip areas.
However, Pittner teaches a semiconductor structure having predetermined pitch (Abstract)[0006][0117].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to have a pitch equal to a minimum pitch in the chip areas as suggested by Pittner in order to yield the predictable result of being able to use a probe card to test the functionality of the chips easily and with good quality ([0116-117] of Pittner).
As to claim 15, An teaches the wafer according to claim 14, comprising, in the frame area:
a bottom layer (210, Fig. 6);
a plurality of conductive fins disposed on the bottom layer (see Fig. 6, 240 shows conductive layers with multiple “conductive fins” on the bottom layer); and
a dielectric layer conformally disposed on the conductive fins (passivation layer 230, Fig. 6);
wherein each of the conductive fins and a portion of the dielectric layer covering thereon forms one of the test fin features (see Fig. 6).
As to claim 16, An teaches the wafer according to claim 15, further comprising, in each of the chip areas:
a main structure (dielectric layer 220, Fig 6, [0061]);
pads disposed on the main structure (150 via contacts Fig. 5, 250 Fig. 6, [0041]); and
a passivation layer (passivation layer 230, Fig. 6) disposed on the pads and the main structure and exposes portions of the pads (see Fig. 6 shows passivation layer 230 exposing portions of the pads);
wherein the conductive fins and the pads are formed of a same material ([0039] teaches fins (conductive layer Fig. 6 240 comprises conductive material, [0047] teaches pads comprise conductive material (via contacts Fig. 6 250)), and
the dielectric layer and the passivation layer are formed of a same material ([0046] teaches silicon nitride for dielectric layer, [0043] teaches silicon nitride for passivation layer.
As to claim 17, the combination teaches the wafer according to claim 16.
An teaches: wherein the conductive fins are formed of Al ([0039] teaches 140/240, Fig. 1 comprises conductive metal such e.g. aluminum).
The combination is silent to: the pads are formed of Al.
However, An teaches that the pads are made of conductive material [0047].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combination to use Al for the conductive material of the pads to yield the predictable result of offering a cost effective yet very efficient and accessible conductive material.
As to claim 18, the combination teaches the wafer according to claim 16, wherein the dielectric layer and the passivation layer are formed of a nitride and an oxide ([0043], [0046]).
As to claim 19, the combination teaches the wafer according to claim 16.
The combination is silent to: wherein the test fin features have a height equal to a sum of a thickness of the pads and a thickness of the passivation layer.
However, the height of the test fin features having a height equal to a sum of a thickness of the pads and a thickness of the passivation layer appears to be a mere recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device (See MPEP 2144 IV).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use try different sizes of fin heights to optimize the wafer functionality.
Response to Arguments
Applicant’s arguments/remarks, (see pages 7-10), filed on 12/05/2025, with respect to the objections have been fully considered and are persuasive. Therefore, the objections has/have been withdrawn.
However, Applicant’s arguments/remarks, with respect to the rejection(s) of claim(s) have been fully considered but are not persuasive.
Applicant’s arguments:
a) Applicant argues the Claim Rejections-35 USC 101, the rejection of claims 1-13 under 35 U.S.C. 101 that claim 1 has been amended according to paragraph [0018], that The feature "the optical characteristic is variation of reflectivity with wavelength" of amended claim 1 is only performed by the optical scatterometer, not by human mental. In view of the amendments, withdrawal of the rejection is respectfully requested.
Examiner's response:
With respect to argument (a), it is respectfully pointed out to applicant that this argument is not persuasive because the feature "scatterometer" as recited in independent claim 1 is a conventional means or system use for data gathering in the technological environment in which to apply a judicial exception and does not amount to significantly more than the exception itself, and thus does not integrate the judicial exception into a practical application.
Further, it is respectfully pointed out to applicant that this argument is not persuasive because claim 1 as amended does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because these are well-understood, conventional activities previously known to the industry (i.e. wherein the optical characteristic is variation of reflectivity with wavelength), recited at a high level of generality. The recitation of the limitations amounts to mere instructions to implement the abstract idea on a computer. As such, there is no inventive concept sufficient to transform the claimed subject matter into a patent-eligible application. The claim does not amount to significantly more than the abstract idea itself. Therefore, claim 1 is ineligible.
As to the dependent claims 2-4, 6 and 8-13 recite mere routine data gathering which is insignificant extra-solution activity per MPEP 2106.05(g)) and do not offer a meaningful limitation. The claims recite generic components configured to implement the same judicial exception, and are rejected for the same as in claim 1.
b) Applicant argues the Claim Rejections-35 USC 103 ……, claims 1-6, 8, 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 6818360 B1 (Phan) in light of US 20090108258 Al (An), and claim 7 is rejected under 35 U.S.C. 103 being unpatentable over US 6818360 BI (Phan) in light of US 20200051875 A1 (Pittner).
Applicant argues that Applicant has amended claim 1 according to claim 7. Amended claim 1 recites:
1. A test method for a wafer, comprising: acquiring data of an optical characteristic ………………………………………. ………………, the optical characteristic is variation of reflectivity with wavelength, and the test key is disposed in the frame area; …... ………………... ………………………………………………………. wherein the test key comprises a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas.
Applicant argues that ……, Phan does not disclose the mask includes a test key comprising a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas.
Examiner's response:
With respect to argument (b), it is respectfully pointed out to applicant that by applicant's own account the rejection was made as 103 not 102 and the amended claim 1 is/are identical to previously presented claims 5 and 7 that were rejected under 35 U.S.C. 103 as being unpatentable over Phan in view of An and Pittner, and the examiner did recognize that the limitation(s) of claim 7 now amended claim 1 was not taught by Phan when modified by An but used Pittner to find this limitation (“…..wherein the test key comprises a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas.”).
Additionally, by applicant's own account (argument (b) above) Phan and An is/are concern with semiconductor/wafer structure and/or device. As such, since the instant application claims and, cited references are reasonably concerned with the semiconductor structure and/or device which the instant applicant is involved, the cited references are considered as an analogous art. As such, it is respectfully pointed out to applicant that it has been held that a prior art reference must either be in the field of applicant's endeavor or, if not, then be reasonably pertinent to the particular problem with which the applicant was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, both the instant application claims and the cited references are reasonably concern semiconductor/wafer structure and/or device, and thus the broadest reason to combine is proper and the currently amended claims are rejected as detailed above.
In addition, it is respectfully pointed out to applicant that these arguments are not persuasive because applicant has not provided any factual evidence that suggest or obviate the examiner's position would not have been obvious, rather applicant's arguments is against the references individually, it is respectfully pointed out to applicant that it is well settled that, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, the examiner did recognize that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992). As shown in the detail above, Phan when modified by An are concerned with semiconductor/wafer structure/device that includes pitches/tranches, and Pittner from the same field of endeavor teaches of a semiconductor structure having predetermined pitch. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Phan when modified by An in view of Pittner to have a pitch equal to a minimum pitch in the chip areas as suggested by Pittner in order to yield the predictable result of being able to use a probe card to test the functionality of the chips easily and with good quality of Pittner), and in order to improve and enhance semiconductor/wafer fabrication, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954). As such, the claims are still rejected as shown in the detail above.
In conclusion, it is respectfully pointed out to applicant that Applicant must show and discuss the references applied against the claims, explaining how the claims avoid the references or distinguish from them. and Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Finally, it is respectfully pointed out to applicant that these arguments are not persuasive because one of ordinary skill before the effective filing date of the claimed invention and/or at the time the invention was made would have fairly and reasonably recognized that the prior art does properly support a rejection of the claimed invention under 35 U.S.C. 103, and the argument/remarks for request for reconsideration does not appear to place the application in condition for allowance.
c) Applicant argues that ……, An does not disclose the features "the test key comprises a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas", as recited in amended claim 1.
Applicant argues that ……, Pittner merely discloses each test electrode has a minimum dimension, not discloses the relationship between the space of the two test electrodes and the distance of the wafer regions. Thus, Pittner fails to disclose "the test key comprises a plurality of test fin features arranged in parallel, the test fin features having a space equal to a minimum space in the chip areas and a pitch equal to a minimum pitch in the chip areas", as recited in amended claim 1.
Applicant argues that ……, Pittner and An can not cure the deficiencies of Phan with respect to the amended claim. It is respectfully submitted that the current-amended independent claim 1 is patentable distinguishable over the cited reference. Claim 14 includes the feature corresponding to that of amended claim 1. Based on the same reason, it is submitted that this application is in condition for allowance and such a Notice, with allowed claim 14 earnestly is solicited.
Examiner's response:
With respect to argument (c), it is respectfully pointed out to applicant that for the same reasons as discussed above in relation to arguments (b), applicant arguments regarding arguments (c) are not persuasive.
In addition, it is respectfully pointed out to applicant that the teachings or suggestions of the prior art that have been used as evidence within a rejection of the claimed invention in view of the prior art under 35 U.S.C. 102 or 35 U.S.C. 103, as set forth by the Court, are to be evaluated and determined not just from one or more specifically identified quotes to individual sections of the text of the prior art document but are in fact to be evaluated and determined from all that the prior art document teaches or suggests, In re BODE et al, 193 USPQ 12 at 17 (CCPA, 1977), with some reliance on the knowledge of one of ordinary skill at the time the invention was made in order to provide an enabling disclosure, In re BODE et al, 193 USPQ 12 at 16 (CCPA, 1977). In view of this, then contrary to Applicant’s arguments to the contrary the Examiner’s need not necessarily point to specific sections of the prior art when supporting a rejection of the claimed invention in view of the prior art under 35 U.S.C. 103.
Finally, Applicant has argued the patentability of claims based solely upon the patentability of independent claim(s), and has presented no additional arguments exclusively pertaining to the dependent claims, since the applicant has not argued the examiner’s position about the rejection(s) regarding the dependent claims, in the previous Official action. The applicant has acquiesced.
Additional Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed in the attached form PTO-892 teach of other prior art test method for a wafer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Isiaka Akanbi whose telephone number is (571) 272-8658. The examiner can normally be reached on 8:00 a.m. - 4:30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Tarifur R. Chowdhury can be reached on (571) 272-2287. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/ISIAKA O AKANBI/Primary Examiner, Art Unit 2877
Prosecution Insights