DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on June 9, 2026 is acknowledged.
Newly submitted claims 21-30 are directed to inventions that are independent or distinct from the invention originally claimed for the following reasons: The inventions of claims 21-30 and the originally claimed invention of claim 1 are directed to related products. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the invention of claims 21-25 is mutually exclusive from the originally claimed invention of claims 1-10 because it can have a materially different design. Specifically, the invention of claim 21 requires a conductive node while the invention of claim 1 does not. Similarly, the invention of claims 26-30 is mutually exclusive from the originally claimed invention of claims 1-10 because it can have a materially different design. Specifically, the invention of claim 26 requires dielectric and insulation layers while claim 1 does not. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-30 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (2023/0058880, hereafter Chang).
Regarding claim 1, Chang discloses a method, comprising: forming a first select transistor (204a, Fig. 4) of a first one-time programmable (OTP) memory bit cell (102a, Fig. 4) over a substrate (par. 0031), wherein the first select transistor is of a first conductivity type (par. 0024); forming a first anti-fuse transistor (202a, Fig. 4) of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type (par. 0024) opposite to the first conductivity type; and forming a bit line (BL0, Fig. 4) over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor (430a, Fig. 4, par. 0033).
Regarding claim 2, Chang discloses a method wherein the first select transistor (204) is an n-type metal- oxide-semiconductor transistor (par. 0024), and the first anti-fuse transistor (202) is a p-type metal-oxide- semiconductor transistor (par. 0024).
Regarding claim 3, Chang discloses a method further comprising: forming a second anti-fuse transistor (202b, Fig. 4) over the substrate, wherein the second anti-fuse transistor is of the second conductivity type (par. 0024) and connected in parallel to the first anti-fuse transistor (par. 0033).
Regarding claim 4, Chang discloses a method wherein the first select transistor (204a) is between the first (202a) and second (202b) anti-fuse transistors from a top view (Fig. 4).
Regarding claim 9, Chang discloses a method further comprising: forming a second OTP memory bit cell (102b, Fig. 4) over the substrate (par. 0031), wherein the second OTP memory bit comprises a second select transistor (204b, Fig. 4) and a second anti-fuse transistor (202b, Fig. 4), and a source/drain terminal (430c, Fig. 4) of the second select transistor is electrically coupled (par. 0033) to the bit line (BL0, Fig. 4).
Regarding claim 10, Chang discloses a method wherein the second select transistor (204) is of the first conductivity type (par. 0024), and the second anti-fuse transistor (202) is of the second conductivity type (par. 0024).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Hou (2023/0363152, hereafter Hou).
Regarding claim 5, Chang fails to disclose a method further comprising: forming a third anti-fuse transistor over the substrate, wherein the third anti-fuse transistor is of the second conductivity type and connected in parallel to the first and second anti-fuse transistors.
However, Hou teaches a method further comprising: forming a third anti-fuse transistor (FG5, Fig. 2) over the substrate, wherein the third anti-fuse transistor is of the second conductivity type (par. 0028) and connected in parallel (par. 0030) to the first (FG7, Fig. 2) and second (FG6, Fig. 2) anti-fuse transistors.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Hou by providing a third anti-fuse transistor of the second conductivity type in order to optimize voltage distribution across the cell which prevents electrical stress through the select transistor.
Regarding claim 6, Chang fails to disclose a method further comprising: forming a second anti-fuse transistor over the substrate, wherein the second anti-fuse transistor is of the first conductivity type and connected in parallel to the first anti-fuse transistor.
However, Hou teaches a method further comprising: forming a second anti-fuse transistor (FG6, Fig. 2) over the substrate, wherein the second anti-fuse transistor is of the first conductivity type (par. 0028) and connected in parallel (par. 0030) to the first anti-fuse transistor (FG7, Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Hou by providing a second anti-fuse transistor in order to decouple high programming voltages from the thin-gate oxides of the logic-compatible transistors, thus suppressing leakage currents and preventing circuitry breakdown.
Regarding claim 7, Chang fails to disclose a method wherein the first anti-fuse transistor is between the first select transistor and the second anti-fuse transistor from a top view.
However, Hou teaches a method wherein the first anti-fuse transistor (FG7) is between the first select transistor (23, par. 0015) and the second anti-fuse transistor (FG6) from a top view (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Hou by providing the first anti-fuse transistor between the select transistor and second anti-fuse transistor in order to create a voltage buffer that shields the select transistor from destructive voltages while optimizing layout by preventing parasitic leakage.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Hou as applied to claims 1-7 above, and further in view of Ning et al. (2023/0422494, hereafter Ning).
Regarding claim 8, Chang fails to disclose a method further comprising: forming a second select transistor of the first OTP memory bit cell over the substrate.
However, Hou teaches a method further comprising: forming a second select transistor (23, Fig. 2, par. 0029) of the first OTP memory bit cell (par. 0023) over the substrate (par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Hou by forming a second select transistor in order to provide voltage blocking capacity or dual gate control.
Chang and Hou fail to disclose the second select transistor is of the first conductivity type.
However, Ning teaches the second select transistor is of the first conductivity type (par. 0078).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Hou by forming a second select transistor in order to provide voltage blocking capacity or dual gate control.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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