DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10-11, 14-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10, 18 define” a circuit including a first FET and a second FET” is indefinite as the specification para [0052] and elected species of Fig. 3A-3B show all three FETs 304, 306, 308 are used to pass the first current and the second current. Appropriate correction is required.
Claims 10 and 18 define “a contiguous gate structure” is unclear which could be interpreted as pieces of bordering gates. A single continuous/contiguous gate structure is suggested as shown in Fig. 2A.
Claim 11 defines “a first FET, a second FET has antecedent issues” which should be the first FET, the second FET.
Claims 11, 14-17, 19-20 are also rejected being dependent on rejected claims 10, 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 14-17 are rejected under 35 U.S.C. 103 as being obvious over Satya et al (US 2008/0006902 A1) in view of Kothandarahman et al. (TS 200415773 A).
Regarding claim 10: Satay teaches in Fig. 5-6 about a bitcell, comprising:
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a fuse field-effect transistor (FET) A (abstract); and
a circuit including a first FET and a second FET, and to (Fig. 5-6):
use the first FET to apply a first signal to pass a first current through a channel of the fuse FET to heat a contiguous gate structure of the fuse FET ([0007] –[ 00008] teaches heat generates because of the current passing through the channel from the source to the drain); and
use the second FET to apply a second signal to pass a second current through the contiguous gate structure between a first gate terminal and a second gate terminal of the fuse FET to permanently degrade one or more electrical characteristics of the fuse FET ([[051] teaches when voltage is applied and therefore a second current passes through WA1 for the fuse FET A causes electromigration (therefore changes electrical characteristics) of the silicide into the channel region, programming the memory element).
Satay does not explicitly show to pass a second current through the contiguous gate structure between a first gate terminal and a second gate terminal of the fuse FET.
Kothandarahman teaches in Fig. 4-6 and abstract about pass a second current through the contiguous gate structure G between a first gate terminal G1/39 and a second gate terminal 41/G2 of the fuse FET.
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Therefore it would have been obvious to a person of ordinary skill in the art at the time of Applicant's was filed to modify Satya’s gate terminal according to the teachings of to have the current pass from a first gate terminal to a second terminal to control the current amount to program the fuse depending on design technology or rule and material types of the FET (Kothandarahman, abstract).
Claims 10, 14-17 are rejected under 35 U.S.C. 103 as being obvious over Satya et al (US 2008/0006902 A1) in view of Kothandarahman et al. (TS 200415773 A)
Regarding claim 14: Satya in view of Kothandarahman does not explicitly talk about wherein the first current is passed concurrently with the second current.
However Satya in Fig. 5-6 and Kothandarahman teaches in Fig. 4-6’s about word lines, bit lines and other control FET’s to operate and program the fuse FET.
The recitation of “the first signal is applied concurrently with the second signal.” does not distinguish the present invention over the prior art of Satya in view of Hsueh who teaches the structure as claimed. The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114.
Regarding claim 15: Satya in view of Kothandarahman does not explicitly talk about wherein the second current is passed after the first current heats the gate of the fuse FET.
However Satya in Fig. 5-6 and Kothandarahman teaches in Fig. 4-6’s about word lines, bit lines and other control FET’s to operate and program the fuse FET.
The recitation of “the second current is passed after the first current” does not distinguish the present invention over the prior art of Satya in view of Hsueh who teaches the structure as claimed. The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114.
Regarding claim 16: As explained in claim 10, Satya in view of Kothandarahman teaches wherein the first current and the second current cause thermal runaway in the gate of the fuse FET (passing currents will cause heat/temperature rise).
Regarding claim 17: Satya teaches in [0051] – [0052] about wherein a read path to read a state of the fuse FET passes through the first gate terminal and the second gate terminal.
Claims 18-20 are rejected under 35 U.S.C. 103 as being obvious over Satya et al (US 2008/0006902 A1) in view of Kothandarahman et al. (TS 200415773 A) and further in view of Huang et al. (US Patent 9153773 B1)
Regarding claim 18: As explained in claim 10, Satya in view of Kothandarahman teaches all the limitations except explicitly talk about non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of the structure.
Huang teaches in col. 7, lines 10-20 about non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of the structure.
Therefore it would have been obvious to a person of ordinary skill in the art at the time of Applicant's was filed to use Huang’s teachings in Satya’s device so that the computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion (Huang, col. 7. Lines 18-20).
Regarding claim 19: As explained in claim 10, Satya in view of Kothandarahman teaches wherein the first current and the second current cause thermal runaway in the gate of the fuse FET (passing currents will cause heat/temperature rise).
Regarding claim 20: As explained in claim 10, Satya in view of Kothandarahman teaches wherein the first current and the second current cause electromigration in the gate of the fuse FET.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein the circuit comprises a first FET, a second FET, and a third FET, wherein a source of the first FET is electrically connected to a drain of the fuse FET, wherein a source of the fuse FET is electrically connected to a drain of the second FET, and the second gate terminal of the gate of the fuse FET is electrically connected to a drain of the third FET” in combination with other limitations as a whole.
Response to Arguments
Applicant’s arguments, see pages 7-8, filed on 08/24/2026, with respect to the rejection(s) of claim(s) 10 under 112, 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new 112 issues and new art Kothandarahman et al. (TS 200415773 A)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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