Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 1-10 in the reply filed on 04/27/2026 is acknowledged. In addition, Applicant has added new claims 21-30, which are also elected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liao et al. (US 20230395427 A1; hereinafter “Liao”).
In re claim 1, Liao discloses in figs. 2-6, a method comprising:
forming a metal pad 125 (fig. 2; ¶40);
depositing a passivation layer 117 on the metal pad 125 (fig. 3; ¶41);
planarizing the passivation layer 117, so that the passivation layer 117 comprises a planar top surface (¶41; “A planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps”);
etching the passivation layer 117 to form an opening (e.g., opening to form plug 127) (hereinafter “OPN”) in the passivation layer 117 (fig. 4; ¶45), wherein the metal pad 125 is exposed to the opening;
forming a conductive via 127 comprising a lower portion (e.g., a portion near the pad 125) in the opening (“OPN”), and an upper portion higher than the passivation layer 127; and
dispensing a polymer layer 143 covering the conductive via 127 (fig. 5; ¶48-49).
In re claim 5, Liao discloses the method of claim 1, the method further comprising, after the passivation layer 117 is planarized and before the passivation layer is etched, depositing a capping layer 141 on the metal pad 125 (fig. 4; ¶43).
Claim(s) 21-24, 27, 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20230088723 A1; hereinafter “Huang”).
In re claim 21, Huang discloses in figs. 2A-2E, a method comprising:
forming a passivation layer 13 comprising:
a first portion (e.g., a portion of the dielectric layer 13 overlapping electrical contacts 11; hereinafter “PAS1”) overlapping a metal pad 11 (fig. 2C; ¶14, 16-17); and
a second portion (e.g., a portion of the dielectric layer 13 not overlapping electrical contacts 11; hereinafter “PAS2”) offset from the metal pad 11,
wherein top surfaces of the first portion PAS1 and the second portion PAS2 are coplanar (fig. 2C);
performing a plating to form a conductive via 14v (fig. 2E, ¶36),
wherein the conductive via 14v comprises:
a lower portion (e.g., a lower portion of 14v that is in the dielectric layer 13; hereinafter “14v_bottom”) in the passivation layer 13; and
an upper portion (e.g., an upper portion of 14v that is over the dielectric layer 13; hereinafter “14v_top”) over the passivation layer 13; and
forming a dielectric layer 13a (figs. 2C; ¶20),
wherein the upper portion of the conductive via 14v_top is in the dielectric layer 13a.
In re claim 22, Huang discloses in figs. 2A-2E, the method of claim 21 further comprising
a forming a pre-layer 12 (fig. 2B; ¶32),
wherein the pre-layer 12 is formed after the metal pad 11 is formed and before the passivation layer 13 is formed, and
wherein the pre-layer 12 comprises a vertical portion and a horizontal portion having a same thickness (the pre-layer 12 is formed conformally on the horizonal and vertical surfaces as shown in fig. 2B. Therefore, a vertical portion and a horizontal portion of the pre-layer 12 have a same thickness. ¶32).
In re claim 23, Huang discloses in figs. 2A-2E, the method of claim 21 further comprising
forming a dielectric capping layer over the passivation layer (fig. 2C; Huang discloses “prior to the formation of the dielectric layer 13a, another promoter may be formed on the dielectric layer 13”; ¶34. This additional promoter layer, like promoter layer 12, has been interpreted as a dielectric capping layer. Hereinafter “Cap”),
wherein the lower portion of the conductive via 14v_bottom is further in the dielectric capping layer Cap.
In re claim 24, Huang discloses in figs. 2A-2E, the method of claim 23, wherein an entirety of the dielectric capping layer Cap is planar (the capping layer is at the interface between dielectric layers 13 and 13a and the interface is shown as a planar interface. Therefore, an entirety of the dielectric capping layer Cap is also planar).
In re claim 27, Huang discloses in figs. 2A-2E, a method comprising:
forming at least one dielectric layer 13, 13a comprising a passivation layer (fig. 2C; ¶34),
wherein the passivation layer 13, 13a comprises:
a first portion (e.g., a portion of the dielectric layer 13, 13a overlapping a leftmost electrical contact 11; hereinafter “PAS1”) overlapping a first metal pad (e.g., left metal pad 11; hereinafter “Pad1”) (fig. 2C; ¶14, 16-17);
a second portion (e.g., a portion of the dielectric layer 13, 13a overlapping middle electrical contact 11; hereinafter “PAS2”) overlapping a second metal pad (e.g., middle metal pad 11; hereinafter “Pad2”) (fig. 2C); and
a third portion (e.g., a portion of the dielectric layer 13, 13a between adjacent metal pads 11, 11; hereinafter “PAS3”) connecting the first portion PAS1 to the second portion PAS2 (fig. 2C),
wherein top surfaces of the first portion PAS1, the second portion PAS2, and the third portion PAS3 are coplanar; and
forming a conductive via 14v, 14 (fig. 2E; ¶36) comprising:
a lower portion 14v in the passivation layer 13, 13a; and
an upper portion 14 over the passivation layer 13, 13a,
wherein the upper portion 14 forms a horizontal interface with a top surface of the first portion of the at least one dielectric layer PAS1.
In re claim 30, Huang discloses in figs. 2A-2E, the method of claim 27, further comprising forming a pre-layer 12 under the passivation layer 13 (fig. 2B; ¶32), wherein the lower portion of the conductive via (i.e., a lower portion of 14v; hereinafter “14v_bottom”) is further in the pre-layer 12.
Claim(s) 21, 25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20220262777 A1; hereinafter “Lee”).
In re claim 21, Lee discloses in figs. 9-18, a method comprising:
forming a passivation layer (e.g., lower insulating layer of the first substrate insulating layer 110; hereinafter “PAS”) (fig. 9; ¶105) comprising:
a first portion (e.g., a first portion of the first insulating layer 110 over the metal pad 124; hereinafter “PAS1”) overlapping a metal pad 124 (¶23); and
a second portion (e.g., a first portion of the first insulating layer 110 not overlapping the metal pad 124; hereinafter “PAS2”) offset from the metal pad,
wherein top surfaces of the first portion PAS1 and the second portion PAS2 are coplanar;
performing a plating to form a conductive via (conductive via comprising 120, 122, 422) (figs. 10-11; ¶44, 107-109),
wherein the conductive via comprises:
a lower portion 120 in the passivation layer PAS; and
an upper portion 122 over the passivation layer PAS; and
forming a dielectric layer (e.g., an upper insulating layer of the first substrate insulating layer 110; hereinafter “DL”),
wherein the upper portion of the conductive via 122 is in the dielectric layer DL.
In re claim 25, Lee discloses in figs. 9-18, the method of claim 21,
wherein the conductive via (120, 122, 422) and the dielectric layer DL are comprised in a device die (a device die comprising layers including first and second device 200, 300, connection layer 120, 122, dielectric layer 110. Hereinafter “Die”) (figs. 10-12; ¶109-1193), and the method further comprises:
encapsulating the device die in an encapsulant 410 (fig. 10; ¶116); and
forming a redistribution structure 500 comprising a plurality of redistribution lines 520 (fig. 12; ¶119),
wherein the plurality of redistribution lines 520 are over and electrically coupled to the device die (Die).
In re claim 26, Lee discloses in figs. 9-18, the method of claim 25, further comprising forming a through-via (another TSV 422) in the encapsulant 410 (figs. 10-11), wherein the through-via 422 is electrically coupled to one of the plurality of redistribution lines 522.
Claim(s) 27, 29 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. (US 20230411275 A1; hereinafter “Kang”).
In re claim 27, Kang discloses in figs. 1-6, 9, a method comprising:
forming at least one dielectric layer 510 comprising a passivation layer (¶72-73),
wherein the passivation layer 510 comprises:
a first portion (e.g., a portion of the base insulating layer 510 over the leftmost metal pad 510; hereinafter “PAS1”) overlapping a first metal pad 524 (¶73, 33);
a second portion (e.g., a portion of the base insulating layer 510 over the second from the left metal pad 510; hereinafter “PAS2”) overlapping a second metal pad 524; and
a third portion (e.g., a portion of the base insulating layer 510 between the two left metal pads 510; hereinafter “PAS3”) connecting the first portion to the second portion,
wherein top surfaces of the first portion PAS1, the second portion PAS2, and the third portion PAS3 are coplanar; and
forming a conductive via 526, 522,416, 414 (¶60, 73) comprising:
a lower portion 526 in the passivation layer 510; and
an upper portion 522, 416, 414 over the passivation layer 510,
wherein the upper portion 522, 416, 414 forms a horizontal interface (e.g., between lower surface of 522 and upper surface of 510) with a top surface of the first portion of the at least one dielectric layer PAS1.
In re claim 29, Kang discloses in figs. 1-6, 9, the method of claim 27.
further comprising forming a dielectric capping layer (e.g., upper layer 510) over the passivation layer (e.g., lower layer 510),
wherein the lower portion of the conductive via 526 is further in the dielectric capping layer (i.e., upper layer 510).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190027451 A1; hereinafter “Kim”) in view of Bonam et al. (US 20210091032 A1; hereinafter “Bonam”).
In re claim 1, Kim discloses in figs. 2-17, a method comprising:
forming a metal pad 211 (fig. 2; ¶34-35);
depositing a passivation layer 213 on the metal pad 211 (fig. 4; ¶39);
etching the passivation layer 213 to form an opening 213H in the passivation layer,
wherein the metal pad 211 is exposed to the opening 213H (fig. 5; ¶43-46);
forming a conductive via 215, 221 comprising a lower portion in the opening, and an upper portion higher than the passivation layer (fig. 6; ¶47); and
dispensing a polymer layer 223 (e.g., a photoimageable dielectric (PID)) covering the conductive via 215, 221 (fig. 8; ¶57-58).
Kim does not expressly disclose planarizing the passivation layer after depositing the passivation layer, so that the passivation layer comprises a planar top surface.
In the same field of endeavor, Bonam discloses in figs. 2-8, a method comprising: planarizing a passivation layer 120 after depositing the passivation layer 120, so that the passivation layer 120 comprises a planar top surface 121 (figs. 4-5; ¶38-40).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to planarize passivation layer after depositing the passivation layer in Kim to form the passivation layer with a planarized surface while maintaining a sufficient thickness of the planarized insulating layer above the metal pads (¶40 of Bonam).
In re claim 6, Kim as modified by Bonam discloses the method of claim 1.
Kim further discloses in figs. 2-17, wherein the etching the passivation layer comprises:
forming a patterned photoresist PM over the passivation layer 213 (fig. 4; ¶41),
wherein the passivation layer 213 is etched using the patterned photoresist PM as an etching mask (fig. 5; ¶42-43).
In re claim 7, Kim as modified by Bonam discloses the method of claim 1.
Kim further discloses in figs. 2-17, wherein the depositing the passivation layer 213 comprises depositing an inorganic dielectric layer (e.g., a silicon oxide layer; ¶40).
In re claim 8, Kim as modified by Bonam discloses the method of claim 1.
Kim further discloses in figs. 2-17, wherein the depositing the passivation layer 213 comprises depositing an additional polymer layer (e.g., photo-imageable dielectric (PID); ¶40).
In re claim 9, Kim as modified by Bonam discloses the method of claim 1.
Kim further discloses in figs. 2-17, wherein the depositing the passivation layer 213 comprises depositing a homogenous material, and an entirety of the passivation layer is formed of the homogenous material (¶40).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bonam, as applied to claim 1 above and further in view of Chen et al. (US 20200135708 A1; hereinafter Chen) and Chen et al. (US 20230275047 A1; Chen’47) (Chen’47 has been listed in the 07/10/2025 IDS).
In re claim 2, Kim, as modified by Bonam, discloses the method of claim 1 outlined above.
Kim, as modified by Bonam, does not expressly disclose the method further comprising:
sawing a wafer comprising the conductive via and the polymer layer to separate a plurality of device dies in the wafer;
encapsulating a device die of the plurality of device dies in an encapsulant; and
polishing the encapsulant and the device die to reveal the conductive via.
In the same field of endeavor, Chen discloses in figs. 1A-1J, a method, wherein:
encapsulating a device die 30b of the plurality of device dies in an encapsulant 31 (fig. 1H; ¶47); and
polishing the encapsulant 31 and the device die 30b to reveal the conductive via 25a (¶47).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the method of Kim/Bonam to protect the chip package from moisture and other foreign materials.
Kim, as modified by Bonam and Chen, does not expressly disclose the method further comprising:
sawing a wafer comprising the conductive via and the polymer layer to separate a plurality of device dies in the wafer.
In the same field of endeavor, Chen’47 discloses in figs. 1-10, a method comprising: sawing a wafer 20 comprising a conductive via 42 (¶21) and a polymer layer 48 (¶23) to separate a plurality of device dies 22 in the wafer (fig. 8; ¶42).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen’47 into the method of Kim/Bonam/Chen such that device dies may be used for bonding to other package components in order to form packages (¶42 of Chen’47).
Claim(s) 3, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bonam, as applied to claim 1 above and further in view of Chen et al. (US 20200135708 A1; hereinafter Chen).
In re claim 3, Kim, as modified by Bonam, discloses the method of claim 1 outlined above.
Kim, as modified by Bonam, does not expressly disclose the method further comprising,
when the metal pad is formed, forming an additional metal pad,
wherein the conductive via is a line via that electrically connects the metal pad to the additional metal pad.
In the same field of endeavor, Chen discloses in figs. 1A-1J, a method, wherein:
when a metal pad 16 is formed, forming an additional metal pad 16 (fig. 1A; ¶15),
wherein a conductive via (22a, V, T) is a line via that electrically connects the metal pad 15 to the additional metal pad 15 (fig. 1I; ¶53-55).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the method of Kim/Bonam to connect adjacent devices and increase functionality of the chip package.
In re claim 10, Kim, as modified by Bonam, discloses the method of claim 1 outlined above.
Kim, as modified by Bonam, does not expressly disclose wherein the depositing the passivation layer comprises depositing a plurality of sub layers comprising different dielectric materials.
In the same field of endeavor, Chen discloses in figs. 1A-1J, a method: wherein the depositing the passivation layer 17 comprises depositing a plurality of sub layers 17a, 17b comprising different dielectric materials (¶17).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the method of Kim/Bonam to enhance moisture blocking and isolation between adjacent contact pads.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bonam, as applied to claim 1 above and further in view of Huang et al. (US 20230088723 A1; hereinafter “Huang”).
In re claim 4, Kim, as modified by Bonam, discloses the method of claim 1 outlined above.
Kim, as modified by Bonam, does not expressly disclose the method further comprising, before the passivation layer is formed, depositing a pre-layer on the metal pad using a conformal deposition process.
In the same field of endeavor, Huang discloses in figs. 2A-2E, a method wherein:
before a passivation layer 13 is formed, depositing a pre-layer 12 on a metal pad 11 using a conformal deposition process (fig. 2B; ¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Huang into the method of Kim/Bonam and form a pre-layer before the passivation layer is formed to enhance the bonding or connection force between the passivation layer and the metal pad, and the delamination issue can be eliminated (¶23 of Huang).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang, as applied to claim 27 above, and further in view of Chen et al. (US 20200135708 A1; hereinafter Chen).
In re claim 28, Kang discloses in figs. 1-6, 9, the method of claim 27 further comprising:
forming an encapsulant 300 contacting opposite sidewalls of the at least one dielectric layer 510 (¶51);
forming a plurality of redistribution lines 440 (¶66) over and electrically coupling to the conductive via 526, 522,416, 414.
Kang does not expressly disclose forming a through-via penetrating through the encapsulant,
forming a plurality of redistribution lines over and electrically coupling to the through-via.
In the same field of endeavor, Chen discloses in figs. 1A-1J, 5, a method wherein:
forming a through-via 60 penetrating through an encapsulant 31 (fig. 5; ¶66-68),
forming a plurality of redistribution lines T over and electrically coupling to the through-via 60.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the method of Kang such that the package structure may further be electrically coupled to another package structure to form a package-on-package (POP) device, enhancing device density and performance.
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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