DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A3, subspecies A3.2 drawn to Fig. 3 and claims 1-16 and 21-23 in the reply filed on 04/29/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/17/2024 and 12/27/2024 has been considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities: it appears extend should be extends. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 8, 9, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. 2022/0181299).
Regarding independent claim 1, Kim teaches a semiconductor structure (Fig. 1, para. 0022+; Fig. 17; para. 0118+), comprising:
a first semiconductor die (200) and a second semiconductor die (100) stacked upon and bonded to one another, the first semiconductor die comprising a first portion and a second portion connected to the first portion, and the first portion being wider than the second portion (Figs. 1, 17);
a capping layer (500) sealing a bonding interface of the first and second semiconductor dies (Figs. 1, 17; para. 0058); and
an insulating encapsulant (800) disposed over the second semiconductor die and covering the first semiconductor die and the capping layer (Fig. 17; para. 0119).
Re claim 6, Kim teaches wherein the first portion of the first semiconductor die is an interconnect (wiring) structure, the second portion of the first semiconductor die is a semiconductor substrate overlying the interconnect structure, and the first semiconductor die further comprises a bonding structure (280’, 240) underlying and wider than the second portion, the bonding structure is electrically coupled to the interconnect structure and the second semiconductor die (Figs. 1, 3; para. 0042-0043, 0050).
Re claim 8, Kim teaches the capping layer comprises a horizontal segment extending along a surface of the second semiconductor die, wherein the surface of the second semiconductor die is substantially coplanar with the bonding interface of the first and second semiconductor dies, and a sidewall of the horizontal segment is substantially coplanar with a sidewall of the second semiconductor die (Figs. 1, 17).
Re claim 9, Kim teaches wherein the bonding interface is free of solder material (para. 0047 – Cu-Cu hybrid bonding is used which does not use solder bumps/material).
Re claim 12, Kim teaches wherein sidewalls of the second semiconductor die, the capping layer, and the insulating encapsulant are substantially coplanar (Fig. 17).
Claim(s) 13 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US 2020/0144172).
Regarding independent claim 13, Chung teaches a semiconductor structure (Fig. 11; para. 0021+), comprising:
a first semiconductor die (50) comprising a first sidewall and a second sidewall laterally displaced from the first sidewall (para. 0021);
a second semiconductor die (100) underlying and bonded to the first semiconductor die (para. 0031);
a capping layer (130, 132, 134, 136) conformally lining the first and second semiconductor dies to seal a bonding interface of the first and second semiconductor dies (para. 0044, 0046); and
an insulating encapsulant (140) covering the first semiconductor die, the second semiconductor die, and the capping layer, the capping layer separating the insulating encapsulant from the first and second semiconductor dies (para. 0048).
Re claim 16, Chung teaches wherein the bonding interface of the first and second semiconductor dies is substantially flat (Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8-12, 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2022/0181299) in view of Chung et al. (US 2020/0144172).
Regarding independent claim 1, Kim teaches a semiconductor structure (Fig. 1, para. 0022+), comprising:
a first semiconductor die (200 or (400 for claim 10)) and a second semiconductor die (100) stacked upon and bonded to one another, the first semiconductor die comprising a first portion and a second portion connected to the first portion, and the first portion being wider than the second portion (Fig. 1);
an insulating encapsulant (500) disposed over the second semiconductor die and covering the first semiconductor die (para. 0058).
Kim is silent with respect to a capping layer.
Chung teaches a semiconductor structure (Fig. 11) including a capping layer (130, 132, 134, 136) sealing a bonding interface of the first and second semiconductor dies (para. 0044, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the capping layer as taught by Chung within the semiconductor structure of Kim to arrive at the claimed invention for the purpose of improving device performance and reducing defects (para. 0044).
Re claim 2, Kim teaches wherein the first semiconductor die comprises:
an interconnect structure underlying a semiconductor substrate (Fig. 2; para. 0032);
a bonding structure (240) underlying the interconnect structure and electrically coupled to the interconnect structure and the second semiconductor die (Fig. 2; para. 0043).
Kim in view of Chung teaches wherein the capping layer conformally extends along the interconnect structure and the bonding structure (Kim Fig. 1, Chung Fig. 11).
Re claim 3, Kim teaches wherein a sidewall of the interconnect structure is laterally offset from a sidewall of the bonding structure (Fig. 2).
Re claim 4, Kim in view of Chung teaches wherein the capping layer further extends along a sidewall of the semiconductor substrate (Kim Fig. 1, Chung Fig. 11).
Re claim 6, Kim teaches wherein the first portion of the first semiconductor die is an interconnect (wiring) structure, the second portion of the first semiconductor die is a semiconductor substrate overlying the interconnect structure, and the first semiconductor die further comprises a bonding structure (280’, 240) underlying and wider than the second portion, the bonding structure is electrically coupled to the interconnect structure and the second semiconductor die (Figs. 1, 3; para. 0042-0043, 0050).
Re claim 8, Kim in view of Chung teaches the capping layer comprises a horizontal segment extending along a surface of the second semiconductor die, wherein the surface of the second semiconductor die is substantially coplanar with the bonding interface of the first and second semiconductor dies, and a sidewall of the horizontal segment is substantially coplanar with a sidewall of the second semiconductor die (Kim Fig. 1, Chung Fig. 11).
Re claim 9, Kim teaches wherein the bonding interface is free of solder material (para. 0047 – Cu-Cu hybrid bonding is used which does not use solder bumps/material).
Re claim 10, Kim is silent with respect to wherein back sides of the first semiconductor die (400) and the insulating encapsulant (500) are substantially coplanar.
Chung teaches a semiconductor structure (Fig. 11) wherein back sides of the first semiconductor die (90) and the insulating encapsulant (140) may be substantially coplanar (para. 0048) or may not be (Fig. 12; para. 0050). That is, both options are known in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the structure of Kim such that the first semiconductor die and the insulating encapsulant such that they were coplanar for the purpose of; for example, providing access to backside connections (Kim para. 0048) or; for example, forming a slimmer package.
Re claim 11, Kim in view of Chung teaches wherein a top surface of the capping layer is substantially coplanar with the back sides of the first semiconductor die and the insulating encapsulant (Kim Fig. 1, Chung Fig. 11).
Re claim 12, Kim in view of Chung teaches wherein sidewalls of the second semiconductor die, the capping layer, and the insulating encapsulant are substantially coplanar (Kim Fig. 1, Chung Fig. 11).
Regarding independent claim 13, Kim teaches a semiconductor structure (Fig. 1; para. 0022+), comprising:
a first semiconductor die (200) comprising a first sidewall and a second sidewall laterally displaced from the first sidewall (Fig. 1);
a second semiconductor die (100) underlying and bonded to the first semiconductor die (Fig. 1);
an insulating encapsulant (500) covering the first semiconductor die, the second semiconductor die (para. 0058).
Kim is silent with respect to a capping layer.
Chung teaches a semiconductor structure (Fig. 11) including a capping layer (130, 132, 134, 136) sealing a bonding interface of the first and second semiconductor dies (para. 0044, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the capping layer as taught by Chung within the semiconductor structure of Kim to arrive at the claimed invention for the purpose of improving device performance and reducing defects (para. 0044).
Re claim 15, Kim teaches wherein the first semiconductor die further comprises a third sidewall laterally displaced from the first and second sidewalls (Fig. 1).
Re claim 16, Kim teaches wherein the bonding interface of the first and second semiconductor dies is substantially flat (Fig. 1).
Claims 1-6, 8-16, 21, and 24 are rejected under 35 U.S.C. 103 as being obvious over Chang et al. (US Pub. 2024/0379482) in view of Chung et al. (US 2020/0144172).
The applied reference has a common Inventor and Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding independent claim 1, Chang teaches a semiconductor structure (Fig. 8; para. 0009+), comprising:
a first semiconductor die (50) and a second semiconductor die (90) stacked upon and bonded to one another, the first semiconductor die comprising a first portion and a second portion connected to the first portion, and the first portion being wider than the second portion (Fig. 8; para. 0026);
an insulating encapsulant (80) disposed over the second semiconductor die and covering the first semiconductor die (para. 0031).
Chang is silent with respect to a capping layer.
Chung teaches a semiconductor structure (Fig. 11) including a capping layer (130, 132, 134, 136) sealing a bonding interface of the first and second semiconductor dies (para. 0044, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the capping layer as taught by Chung within the semiconductor structure of Kim to arrive at the claimed invention for the purpose of improving device performance and reducing defects (para. 0044).
Re claim 2, Chang teaches wherein the first semiconductor die comprises: an interconnect structure underlying a semiconductor substrate; a bonding structure underlying the interconnect structure and electrically coupled to the interconnect structure and the second semiconductor die (para. 0 11).
Chang in view of Chung teaches wherein the capping layer conformally extends along the interconnect structure and the bonding structure (Chung Fig. 8, Chang Fig. 11).
Re claim 3, Chang teaches wherein a sidewall of the interconnect structure is laterally offset from a sidewall of the bonding structure (Fig. 8).
Re claim 4, Chang in view of Chang teaches the capping layer further extend along a sidewall of the semiconductor substrate (Chung Fig. 8, Chang Fig. 11).
Re claim 5, Chang in view of Chung teaches the capping layer comprises a first vertical segment extending along a sidewall of the second portion of the first semiconductor die, a first horizontal segment connected to the first vertical segment and extending along an upper surface of the first portion of the first semiconductor die, a second vertical segment connected to the first horizontal segment and extending along a first sidewall of the first portion of the first semiconductor die, a second horizontal segment connected to the second vertical segment and extending along a lower surface of the first portion of the first semiconductor die, and a third vertical segment connected to the second horizontal segment and extending along a second sidewall of the first portion of the first semiconductor die (Chung Fig. 8, Chang Fig. 11).
Re claim 6, Chang teaches the first portion of the first semiconductor die is an interconnect structure, the second portion of the first semiconductor die is a semiconductor substrate overlying the interconnect structure, and the first semiconductor die further comprises a bonding structure underlying and wider than the second portion, the bonding structure is electrically coupled to the interconnect structure and the second semiconductor die (Fig. 8; para. 0011).
Re claim 8, Chang in view of Chung teaches the capping layer comprises a horizontal segment extending along a surface of the second semiconductor die, wherein the surface of the second semiconductor die is substantially coplanar with the bonding interface of the first and second semiconductor dies, and a sidewall of the horizontal segment is substantially coplanar with a sidewall of the second semiconductor die (Chung Fig. 8, Chang Fig. 11).
Re claim 9, Chang teaches wherein the bonding interface is free of solder material (para. 0029).
Re claim 10, Chang in view of Chung teaches wherein back sides of the first semiconductor die and the insulating encapsulant are substantially coplanar (Chung Fig. 8, Chang Fig. 11).
Re claim 11, Chang in view of Chung teaches wherein a top surface of the capping layer is substantially coplanar with the back sides of the first semiconductor die and the insulating encapsulant (Chung Fig. 8, Chang Fig. 11).
Re claim 12, Chang in view of Chung teaches wherein sidewalls of the second semiconductor die, the capping layer, and the insulating encapsulant are substantially coplanar (Chung Fig. 8, Chang Fig. 11).
Regarding independent claim 13, Chang teaches a semiconductor structure (Fig. 8; para. 0009+), comprising:
a first semiconductor die (50; para. 0009) comprising a first sidewall and a second sidewall laterally displaced from the first sidewall (Fig. 8);
a second semiconductor die (90) underlying and bonded to the first semiconductor die (para. 0090);
an insulating encapsulant (80) covering the first semiconductor die, the second semiconductor die (para. 0031).
Chang is silent with respect to a capping layer.
Chung teaches a semiconductor structure (Fig. 11) including a capping layer (130, 132, 134, 136) sealing a bonding interface of the first and second semiconductor dies (para. 0044, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the capping layer as taught by Chung within the semiconductor structure of Kim to arrive at the claimed invention for the purpose of improving device performance and reducing defects (para. 0044).
Re claim 14, Chang teaches wherein the first sidewall of the first semiconductor die is smoother than the second sidewall of the first semiconductor die (para. 0019).
Re claim 15, Chang teaches wherein the first semiconductor die further comprises a third sidewall laterally displaced from the first and second sidewalls (Fig. 8).
Re claim 16, Chang teaches wherein the bonding interface of the first and second semiconductor dies is substantially flat (Fig. 8).
Regarding independent claim 21, Chang teaches a semiconductor structure (Fig. 8; para. 0009+), comprising:
a first semiconductor die (50) comprising: a semiconductor substrate; a first bonding structure disposed below the semiconductor substrate; and an interconnect structure comprising a first portion interfaced with the semiconductor substrate, a second portion interfaced with the first bonding structure, and a third portion interposed between and wider than the first and second portions (Fig. 8; para. 0011); and
a second semiconductor die (90) comprising a second bonding structure bonded to the first semiconductor die (para. 0026);
an insulating encapsulant (80) laterally surrounding the first semiconductor die (para. 0031).
Chang is silent with respect to a capping layer.
Chung teaches a semiconductor structure (Fig. 11) including a capping layer (130, 132, 134, 136) sealing a bonding interface of the first and second semiconductor dies (para. 0044, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the capping layer as taught by Chung within the semiconductor structure of Kim to arrive at the claimed invention for the purpose of improving device performance and reducing defects (para. 0044).
Re claim 24, Chang teaches wherein a sidewall of the first portion of the interconnect structure is substantially coplanar with a sidewall of the semiconductor substrate, and a sidewall of the second portion of the interconnect structure is substantially coplanar with a sidewall of the first bonding structure (Fig. 8).
Claim 22 is rejected under 35 U.S.C. 103 as being obvious over Chang et al. (US Pub. 2024/0379482) in view of Chung et al. (US 2020/0144172) and further in view of Official Notice.
The applied reference has a common Inventor and Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Re claim 22, Chang and Chung are silent with respect to a seal ring.
The Examiner is taking Official Notice that seal ring structures formed from the interconnect structure and disposed in a peripheral region of a die are known in the art for the purpose of providing protection to the device during dicing/sawing and preventing moisture intrusion and it would have been obvious to one of ordinary skill in the art at the time of filing to include a seal ring within the device of Chang to arrive at the claimed invention for the same advantages.
Allowable Subject Matter
Claims 7 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: there is no teaching, suggestion, or motivation from the prior art of record, nor does the prior art of record otherwise make obvious the limitations of…
Re claim 7, …and the capping layer is in physical contact with the seal ring…
Re claim 23, …wherein the capping layer is interfaced with a surface of the seal ring…
…in combination with the other limitations.
Conclusion
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/MOLLY K REIDA/Examiner, Art Unit 2899
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