DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims including where claim 1 recites the first portion of the insulating encapsulant laterally encapsulates the second semiconductor die. Applicant’s drawings show (FIG. 9-10) the first portion of the insulating encapsulant (140) adjacent to but not laterally encapsulating the second semiconductor die (260). The term “encapsulate” is commonly understood to mean to enclose in as if in a capsule, and a structure which does not cover the at least both lateral surfaces in cross-section would not be interpreted by one having ordinary skill in the art to be “laterally encapsulating”. Although not currently claimed, specifying that the first portion of the encapsulant (140) is laterally adjacent to a sidewall of the second semiconductor die (260) would resolve the drawings objection.
The claimed features must be shown or the feature(s) canceled from the claim(s) and no new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-12, in the reply filed on 05/22/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites “wherein the first conductive terminals” but claim 6 depends on claim 5 which depends on claim 3 which depends on claim 1 which together fails to provide antecedent basis for the first conductive terminals. The limitation of the first conductive terminals is introduced in claim 2 but claim 6 does not depend either directly or indirectly from claim 2. For purposes of examination, “the first conductive terminals” is interpreted as “first conductive terminals”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3,7-11 are rejected under 35 U.S.C. § 103 as being unpatentable over US 2024/0079285 A1 to Kang et al., “Kang”, in view of US 2021/0043604 A1 to Fang, “Fang”.
Regarding claim 1, Kang discloses a structure (e.g. FIG. 1), comprising:
an interposer substrate (100, ¶ [0020]);
a first semiconductor die (300, ¶ [0022]-[0026]) disposed on the interposer substrate (100);
a second semiconductor die (400, ¶ [0031],[0032]) disposed on the interposer substrate (100);
an underfill (340, ¶ [0027]) disposed between the first semiconductor die (300) and the interposer substrate (100); and
an insulating encapsulant (500, ¶ [0033]-[0036]) disposed on the interposer substrate (100), wherein the insulating encapsulant (500) comprises a first portion (e.g. upper portion on 300, see Examiner-annotated figure below) and a second portion (lower portion adjacent 400), the first portion covers the second portion, the first portion laterally encapsulates the first semiconductor die (300), and the second portion is disposed between the second semiconductor die (400) and the interposer substrate (100).
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Although Kang teaches wherein the first portion (upper portion of 500) is in proximity to the side of the second semiconductor die (400), Kang fails to clearly teach wherein the first portion laterally encapsulates the second semiconductor die (400).
Fang teaches (e.g. FIG. 3(a)) wherein a first portion of an insulating encapsulant (103, ¶ [0035]) laterally encapsulates (wherein the language “laterally encapsulates” is interpreted as laterally surrounding in cross-section but not necessarily contacting) a second semiconductor die (102, ¶ [0034]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang with the first portion of the insulating encapsulant (500) laterally encapsulating the second semiconductor die (400) as taught by Fang in order to desirably encapsulate the resulting package and obtain better heat dissipation environment (Fang ¶ [0003],[0004]) while allowing for the second semiconductor die to the detected as failure (or pass) thereby reducing the yield loss of the semiconductor package (Fang ¶ [0003],[0004],[0038]).
Regarding claim 2, Kang in view of Fang yields the structure of claim 1, and Kang further teaches wherein the first semiconductor die (300) is electrically connected to the interposer substrate (100) via first conductive terminals (330, ¶ [0024],[0025]) between a top surface of the interposer substrate (100) and a bottom surface of the first semiconductor die (300).
Regarding claim 3, Kang in view of Fang yields the structure of claim 1, and Kang further teaches wherein the second semiconductor die (400) is electrically connected to the interposer substrate (100) via second conductive terminals (230, ¶ [0030]) between the top surface of the interposer substrate (100) and a bottom surface of the second semiconductor die (400).
Regarding claim 7, although Kang in view of Fang yields the structure of claim 1, Kang fails to clearly teach wherein a top surface of the first portion (of 500) substantially levels with a top surface of the first semiconductor die (300).
However, Fang further teaches (FIG. 3(a)) wherein a top surface of a first portion (of 103) is substantially level (¶ [0040]) with a top surface of a first semiconductor die (101).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang in view of Fang with the top surface of the first portion level with the first semiconductor die as taught by Fang in the process of encapsulating the resulting package and obtain better heat dissipation environment (Fang ¶ [0003],[0004]).
Regarding claim 8, Kang discloses a structure (e.g. FIG. 1), comprising:
an interposer substrate (100, ¶ [0020]);
a first semiconductor die (300, ¶ [0022]-[0026]) disposed on the interposer substrate (100), the first semiconductor die (300) comprising first conductive terminals (330, ¶ [0024],[0025]);
a second semiconductor die (400, ¶ [0031],[0032]) disposed on the interposer substrate (100), the second semiconductor die (400) comprising second conductive terminals (230, ¶ [0030]); and
an insulating encapsulant (500, ¶ [0033]-[0036]) disposed on the interposer substrate,
wherein the insulating encapsulant laterally encapsulates the first semiconductor die (300) and the second conductive terminals (230).
Although Kang teaches wherein the first portion (upper portion of 500) is in proximity to the side of the second semiconductor die (400), Kang fails to clearly teach wherein the first portion laterally encapsulates the second semiconductor die (400).
Fang teaches (e.g. FIG. 3(a)) wherein a first portion of an insulating encapsulant (103, ¶ [0035]) laterally encapsulates (wherein the language “laterally encapsulates” is interpreted as laterally surrounding in cross-section but not necessarily contacting) a second semiconductor die (102, ¶ [0034]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang with the first portion of the insulating encapsulant (500) laterally encapsulating the second semiconductor die (400) as taught by Fang in order to desirably encapsulate the resulting package and obtain better heat dissipation environment (Fang ¶ [0003],[0004]) while allowing for the second semiconductor die to the detected as failure (or pass) thereby reducing the yield loss of the semiconductor package (Fang ¶ [0003],[0004],[0038]).
Regarding claim 9, Kang in view of Fang yields the structure of claim 8, and Kang further discloses an underfill (340, ¶ [0027]) disposed between the first semiconductor die (300) and the interposer substrate (100), wherein the insulating encapsulant (500) is spaced part from the first conductive terminals (330) by the underfill (340).
Regarding claim 10, Kang in view of Fang yields the structure of claim 9, and Kang further discloses wherein the insulating encapsulant (500) is in contact (FIG. 4) with the second conductive terminals (230) and (FIG. 1) the underfill (340).
Regarding claim 11, Kang in view of Fang yields the structure of claim 9, and Kang further discloses (FIG. 1) wherein the first conductive terminals (330) are spaced laterally apart from each other by the underfill (340), and the second conductive terminals (230) are spaced laterally apart from each other by the insulating encapsulant (500).
Claims 4-6,12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0079285 A1 to Kang et al., “Kang”, in view of US 2021/0043604 A1 to Fang, “Fang”, as applied to claims 2,3, and 8 above, and further in view of US 9,646,942 B2 to Lin et al., “Lin”.
Regarding claim 4, Kang in view of Fang yields the structure of claim 2, and although Kang teaches wherein the first conductive terminals (330) may include solder balls or solder bumps (Kang ¶ [0025]), Kang fails to clearly teach together wherein the first conductive terminals (330) comprise first conductive bumps contacting the top surface of the interposer substrate, second conductive bumps in contact with the bottom surface of the first semiconductor die, and solder regions between the first conductive bumps and the second conductive bumps.
Lin teaches (e.g. FIG. 1) wherein conductive terminals (31, 51, and 53 together, column 2 lines 48-55) comprise first conductive bumps (31) (indirectly) contacting the top surface of an interposer substrate (30, column 2 lines 27-47), second conductive bumps (51) in (indirect) contact with the bottom surface of a semiconductor die (50), and solder regions (53) between the first conductive bumps and the second conductive bumps.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang in view of Fang with the conductive terminals formed by bumps connected by solder as taught by Lin in order to desirably adjust and tune the stand-off distance and to keep bump heights constant (Lin Abstract, column 2 lines 48-55, column 4 line 33 to column 5 line 47).
Regarding claim 5, Kang in view of Fang yields the structure of claim 3, and although Kang teaches wherein the second conductive terminals (230) may include solder balls or solder bumps (¶ [0030]), Kang fails to clearly teach together wherein the second conductive terminals (230) comprise first conductive pillars contacting the top surface of the interposer substrate, second conductive pads contacting the bottom surface of the second conductive die, and solder regions between the first conductive pillars and the second conductive pads.
Lin teaches (e.g. FIG. 1) wherein conductive terminals (31, 51, and 53 together, column 2 lines 48-55) comprise first conductive pillars (31) (indirectly) contacting the top surface of an interposer substrate (30, column 2 lines 27-47), second conductive pads (51) in (indirect) contact with the bottom surface of a semiconductor die (50), and solder regions (53) between the first conductive pillars and the second conductive pads.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang in view of Fang with the conductive terminals formed by bumps connected by solder as taught by Lin in order to desirably adjust and tune the stand-off distance and to keep bump heights constant (Lin Abstract, column 2 lines 48-55, column 4 line 33 to column 5 line 47).
Examiner’s Note: Applicant uses the terms “conductive bumps” and “conductive pillars” and “conductive pads” to refer to items which appear to be similar shaped squares in cross-section. Applicant has not expressly defined the terms bump/pillar/pad the terms are therefore the terms are interpreted under the doctrine of broadest reasonably interpretation (BRI, MPEP 2111) as generally conductive columns suitable for interfacing with a semiconductor die and/or interposer and suitable for applying reflow solder to join together.
Regarding claim 6 insofar as definite, although Kang in view of Fang and Lin yields the structure of claim 5, and Lin further teaches (FIG. 1) wherein the first conductive terminals (31, 51, and 53 together) are higher (distance S) than first conductive pillars (e.g. 31 alone).
Kang as modified by Fang and Lin fails to clearly anticipate wherein a top surface of the first conductive bumps substantially levels with a top surface of the first conductive pillars.
However, Kang teaches wherein first conductive terminals (e.g. 330 on left near boundary between R1 and R2) are in proximity to second conductive terminals (230 on right near boundary of R2 with R1).
Lin teaches (e.g. FIG. 3B,3C) wherein heights of top surfaces of conductive terminals or conductive bumps (250) are all substantially level.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang in view of Fang and Lin with the top surfaces of the first conductive bumps and first conductive pillars at substantially the same level as suggested by Lin since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the heights determine the relative standoff distance (e.g. Lin FIG. 3A) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 12, although Kang in view of Fang yields the structure of claim 8, Kang fails to clearly teach in sufficient detail for anticipation wherein the interposer substrate (100) comprises a semiconductor substrate, a redistribution structure and conductive terminals, the redistribution structure is electrically connected to the semiconductor substrate, the conductive terminals are electrically connected to the redistribution structure, and wherein the conductive terminals and the semiconductor substrate are disposed on opposite sides of the redistribution structure.
Lin teaches (e.g. FIG. 1, column 2 lines 27-47) wherein an interposer substrate (30) comprises a semiconductor substrate (column 2 lines 30-32), a redistribution structure (FIG. 1 traces connected to 15) and conductive terminals (15), the redistribution structure is electrically connected to the semiconductor substrate, the conductive terminals (15) are electrically connected to the redistribution structure (traces connected to 15), and wherein the conductive terminals (15) and the semiconductor substrate (30) are disposed on opposite sides of the redistribution structure.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kang in view of Fang as applied to an interposer substrate as exemplified by Lin in order to achieve a package integrated circuit (Lin column 2 lines 27-30) and/or an interposer substrate with the improved integration of multiple chips and durability of Kang (Kang ¶ [0003],[0036],[0082],[0086],[0087]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2025/0062172 A1 to Shim teaches (e.g. FIG. 4) integrating first (200) and second (300) semiconductor dies with an encapsulant (410);
US 2018/0090449 A1 to JEONG et al. teaches (FIG. 1) wherein a first encapsulant (140) is formed between a second semiconductor die (130) and an interposer (112);
US 2019/0237454 A1 to Hou et al. teaches (FIG. 23,24) encapsulating a first semiconductor die (1701) and removing a dummy element (2203) to form a second semiconductor die (2401);
US 2023/0352468 A1 to Jin teaches (e.g. FIG. 7) integrating first and second semiconductor dies (300, 500) on an interposer (110);
US 2020/0203309 A1 to Beyne teaches (FIG. 1F,1G) encapsulating a first semiconductor die (4) and encapsulating (11) and then forming a second semiconductor die (13) on an interposer (3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
Prosecution Insights