Prosecution Insights
Last updated: October 04, 2026
Application No. 18/415,613

MICRO-ELECTRO-MECHANICAL SYSTEM PACKAGE AND FABRICATION METHOD THEREOF

Non-Final OA §102§103
Filed
Jan 17, 2024
Examiner
ANDERSON, WILLIAM H
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Vanguard International Semiconductor Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
188 granted / 221 resolved
+17.1% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
46 currently pending
Career history
261
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
52.9%
+12.9% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 221 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (a product made) in the reply filed on 5/22/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/22/2026. Information Disclosure Statement The information disclosure statement (IDS) submitted on 9/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claim 10 is objected to because of the following informalities: “the second device portion, the first device portion, the first peripheral portion and the second peripheral portion” in lines 4-5. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “the second device portion, the first device portion, the first peripheral portion and the second peripheral portion” is found to be a typographical error and is believed to be equivalent to “the second device portion; the first device portion, the first peripheral portion and the second peripheral portion” based on Fig. 1 showing dimensions and arrangements consistent with this grouping of terms; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4, 6-7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20200024136 A1). Regarding claim 1, Lee discloses a micro-electro-mechanical system (MEMS) package (Fig. 14), comprising: a wafer (202) with an interconnect layer (204); a first device layer (206 at 104A) comprising a first MEMS device (104A; [0017]: “MEMS device”) having a first thickness (vertical thickness, See annotated figure for dashed thickness reference lines A-C), disposed on the wafer (vertically indirectly “on”) and bonded (indirectly “bonded”) to the interconnect layer; a second device layer (206 at 104B) comprising a second MEMS device (104B; [0017]: “MEMS device”) having a second thickness (vertical thickness, See annotated figure for dashed thickness reference lines A-B) thinner than the first thickness (vertically “thinner”), laterally (See annotated figure for direction designation) spaced apart from the first device layer (“spaced apart” by at least some distance), disposed on the wafer (vertically indirectly “on”) and bonded (indirectly “bonded”) to the interconnect layer; a raised electrode (See annotated figure; [0017]: “metallization planes”), disposed above (directly vertically “above”) the interconnect layer and directly below (vertically “below”) the second MEMS device (Note: the raised electrode reaches exactly the same vertical level as the device 104B, this is directly below because there is no intervening vertical level between these structures.); a first cap substrate (106 at 104A) with a first cavity (C1), bonded to the first device layer (“bonded” by 208 on left), wherein the first MEMS device corresponds to the first cavity (this is the designation cited above); and a second cap substrate (106 at 104B) with a second cavity (C2), laterally spaced apart from the first cap substrate (“spaced apart” by at least some distance), and bonded to the second device layer (“bonded” by 208 on right), wherein the second MEMS device corresponds to the second cavity (this is the designation cited above). Illustrated below is a marked and annotated figure of Fig. 14 of Lee. PNG media_image1.png 387 584 media_image1.png Greyscale Regarding claim 2, Lee discloses the MEMS package of claim 1 (Fig. 14), further comprising: a dielectric layer (See annotated figure; [0017]: “an inter-metal dielectric”), disposed between (vertically “between”) the raised electrode and the interconnect layer; and a via (See annotated figure; [0017]: “vias”), passing through the dielectric layer (vertically “through”) and electrically connecting the raised electrode to the interconnect layer ([0017]: “electrically coupled to the semiconductor devices”). Regarding claim 4, Lee discloses the MEMS package of claim 2 (Fig. 14), wherein the raised electrode and the dielectric layer have the same pattern in a top view (these features have the same lateral footprint, and thus “have the same pattern in a top view”). Regarding claim 6, Lee discloses the MEMS package of claim 1 (Fig. 14), wherein the interconnect layer comprises a top metal layer (See annotated figure), a portion of the top metal layer is exposed (“exposed” to cavity C1) through an opening (“an opening” of 204) and located directly below (vertically “below”) the first MEMS device, a first gap (See annotated figure for dashed arrow) is between the portion of the top metal layer and the first MEMS device, a second gap (See annotated figure for dashed arrow) is between the raised electrode and the second MEMS device, and the second gap is smaller (vertically “smaller”) than the first gap. Illustrated below is a marked and annotated figure of Fig. 14 of Lee. PNG media_image2.png 387 584 media_image2.png Greyscale Regarding claim 7, Lee discloses the MEMS package of claim 1 (Fig, 14), wherein the first MEMS device comprises an accelerometer ([0017]: “the first MEMS device 104A includes an accelerometer”), the second MEMS device comprises a gyroscope ([0017]: “the second MEMS device 104B includes a gyroscope”), the first cavity has a first pressure (P1), and the second cavity has a second pressure (P2) lower than the first pressure ([0030]: “P1 is atmospheric pressure…P2 is a vacuum in comparison to atmospheric pressure”). Regarding claim 10, Lee discloses the MEMS package of claim 1 (Fig. 14), wherein the first device layer comprises a first device portion (See 1st annotated figure) and a first peripheral portion (See 1st annotated figure) abutting (laterally “abutting”) the first device portion, the second device layer comprises a second device portion (See 1st annotated figure) and a second peripheral portion (See 1st annotated figure) abutting (laterally “abutting”) the second device portion, the first device portion, the first peripheral portion and the second peripheral portion have the first thickness (vertical thickness, See annotated figure for dashed thickness reference lines A-C), and the second device portion has the second thickness (vertical thickness, See annotated figure for dashed thickness reference lines A-B). Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kizhakkeyil (US 20250230037 A1). The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 1, Kizhakkeyil discloses a micro-electro-mechanical system (MEMS) package (Fig. 1), comprising: a wafer (130) with an interconnect layer (132); a first device layer (120A) comprising a first MEMS device (121) having a first thickness (T1), disposed on the wafer (“on” in the Z direction) and bonded to the interconnect layer (“bonded” by 127); a second device layer (120B) comprising a second MEMS device (122) having a second thickness (T2) thinner than the first thickness ([0022]: “thinner than a first thickness”), laterally spaced apart (“spaced apart” in the X direction) from the first device layer, disposed on (“on” in the Z direction) the wafer and bonded (“bonded” by 127) to the interconnect layer; a raised electrode (See annotated figure; [0023]: “the top metal layer”), disposed above (“above” in the Z direction) the interconnect layer and directly below (“below” in the Z direction) the second MEMS device; a first cap substrate (110A) with a first cavity (111), bonded (“bonded” by 115) to the first device layer, wherein the first MEMS device corresponds to the first cavity; and a second cap substrate (110B) with a second cavity (112), laterally spaced apart (“spaced apart” in the X direction) from the first cap substrate, and bonded (“bonded” by 115) to the second device layer, wherein the second MEMS device corresponds to the second cavity (this is the designation relied upon by the citations above). Illustrated below is a marked and annotated figure of Fig. 1 of Kizhakkeyil. PNG media_image3.png 527 790 media_image3.png Greyscale Regarding claim 8, Kizhakkeyil discloses the MEMS package of claim l (Fig.1), wherein the second device layer comprises a recessed portion (See annotated figure, “recessed” because of 125B) facing towards (“towards” in the Z direction) the interconnect layer, and the raised electrode is located in the recessed portion (“located in” by occupying an X direction footprint of the recessed portion). Regarding claim 9, Kizhakkeyil discloses the MEMS package of claim 8 (Fig.1), further comprising: a first bond seal ring (125A), disposed between (“between” in the Z direction) the first device layer and the wafer, and bonded to the interconnect layer (“bonded” by 127); and a second bond seal ring (125B), disposed between (“between” in the Z direction) the second device layer and the wafer, and bonded to the interconnect layer (“bonded” by 127), wherein a sidewall of the recessed portion is vertically aligned (“aligned” along the Z direction) with an inner sidewall of the second bond seal ring. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20170297902 A1). Regarding claim 5, Lee discloses the MEMS package of claim 2 (Fig. 14), wherein the raised electrode is located directly below (vertically “below”. Note: the raised electrode reaches exactly the same vertical level as the device 104B, this is directly below because there is no intervening vertical level between these structures.) a proof mass ([0017]: “gyroscope”. Note: a MEMS gyroscope necessarily has a proof mass to render an operable device, MPEP 2144.03. See additional remarks below.) of the second MEMS device. Lin teaches a proof mass ([0024]: “proof mass”) of the second MEMS device ([0024]: “MEMS device”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed “proof mass” because it is a component required to render an operable known device that is otherwise known (Lin: [0024]: “gyroscope”; Lee: [0017]: “gyroscope”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed “proof mass” because it a known component required to render a similar operable known device. MPEP 2144.03. Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the allowable subject matter of claim 3 is the inclusion of the limitation “wherein a difference between the first thickness and the second thickness is greater than a thickness of the dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first thickness”, “second thickness”, “difference”, and “greater than” in combination with all other limitations in claims 3, 2, and 1. The claimed dimensions were not disclosed in the prior art of record, and teachings elsewhere in the prior art fail to teach or render obvious the claimed dimensional relation. MPEP 2144.04 (IV); MPEP 2144.05 (I) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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Prosecution Timeline

Jan 17, 2024
Application Filed
Aug 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+17.9%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 221 resolved cases by this examiner. Grant probability derived from career allowance rate.

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