DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Examiner notes the response to the election filed 07 JUL 2026. Examiner withdraws the requirement for the election of species as previously presented as said species appear to be allowable subject matter in the context of the claims as currently presented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung ‘570 (US PGPub 2020/0020570) in view of McSwiney ‘885 (US PGPub 2005/0025885).
Claim 1 – Sung ‘570 teaches a method for forming a semiconductor structure, comprising:
forming a semiconductor device over a substrate (PG 0039);
forming a trench in the semiconductor device (PG 0043); and
filling the trench with a gap-fill material using a deposition process (PG 0045, silicon nitride “conformally deposited”).
Sung ‘570 does not expressly teach or suggest wherein a precursor used in the deposition process comprises azidosilane, di-azidosilane or halide azidosilane.
McSwiney ‘885 discloses a method for low-temperature silicon nitride deposition (Title, Abstract, PG 0016) and discloses that azidosilanes are known to be suitable precursors for said deposition (PG 0051). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made or filed to have modified the invention of Sung ‘570 to use deposition precursors comprising azidosilanes to deposit silicon nitride as suggested by McSwiney ‘885, as Sung ‘570 wants to deposit silicon nitride and McSwiney ‘885 teaches that azidosilanes are known to be suitable precursors for silicon nitride deposition.
Claim 7 – Sung ‘570 / McSwiney ‘885 renders obvious the method according to claim 1, wherein a width of the trench is in a range of 3nm to 150nm, and a depth of the trench is in a range of 15nm to 300nm. Selection of suitable dimensions for semiconductor features is held as a prima facie obvious design choice absent critical or unexpected results derived from the selection.
Allowable Subject Matter
Claims 2-6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As regards Claim 2, the cited azidosilanes are not found for use in the context of the present invention.
As regards Claim 3, azidosilanes are not found for use in the context of flowable CVD as required by the claim.
As regards Claim 4, there is no evidence that the cited azidosilane precursor undergoes the Curtius rearrangement as required.
As regards Claims 5 and 6, curing processes on silicon nitride depositions commensurate with Claim 1 are not found for use in the context of the present invention.
As regards Claim 8, Sung ‘580 discloses secondary trench formations at PG 0047 with deposition of a gate dielectric (silicon nitride is a known gate dielectric), and McSwiney ‘885 discloses ALD deposition of silicon nitride at PG 0016; however, halide azidosilane is not contemplated for this purpose in the prior art.
Claims 9-17 and 21-23 are allowed.
The following is an examiner’s statement of reasons for allowance:
Sung ‘570 / McSwiney ‘885 is held to be the closest prior art to Claim 9. The broad steps of the method of Claim 9 are disclosed in Sung ‘580: forming a semiconductor device over a substrate (PG 0036-0048), the semiconductor device comprising a plurality of nanostructures (PG 0039, dummy gates 116), source/drain structures aside the plurality of nanostructures (PG 0048, S/D contacts on adjacent active gates), gate structures around the plurality of nanostructures (PG 0039, active gates 114 interspersed between dummy gates 116), and contact structures above the source/drain structures (PG 0048, capping layer 152); patterning the semiconductor device to form a trench (PG 0043), and filling the trench with a gap-fill material (PG 0045); and patterning the semiconductor device to form a second trench (PG 0046, part of barrier layer 144 must be removed before second ILD layer 146 can be placed), and forming liner structures on sidewalls of the second trench (PG 0046). McSwiney ‘885 discloses the silicon nitride deposition process using e.g. azidosilanes at PG 0016 and 0051 and renders ALD obvious for the second deposition process. However, the required timing of steps in Sung ‘580 does not directly line up with the claim, flowable CVD is not disclosed for the first deposition, and the azidosilane precursor disclosed by McSwiney ‘885 is not disclosed as undergoing the Curtius rearrangement in either deposition process. This combination of discrepancies, coupled with the other limitations of Claim 9, set Claim 9 and dependents clear of the prior art.
Sung ‘570 / McSwiney ‘885 is held to be the closest prior art to Claim 21. The broad steps of the method of Claim 9 are disclosed in Sung ‘580: forming a plurality of transistors (PG 0036, FinFET), comprising: forming a plurality of nanostructures (PG 0039, dummy gates 116), forming source/drain structures aside the plurality of nanostructures (PG 0048, S/D contacts on adjacent active gates), forming gate structures around the plurality of nanostructures (PG 0039, active gates 114 interspersed between dummy gates 116), forming contact structures above the source/drain structures (PG 0048, capping layer 152); and forming a gap-fill material located aside the gate structure above the source/drain structures (PG 0048 in combination with McSwiney ‘885 PG 0016, ALD deposition of the capping layer allows the upper layers of this deposition to read on that structure). McSwiney ‘885 discloses the silicon nitride deposition process using e.g. azidosilanes at PG 0016 and 0051 and renders ALD obvious for the deposition process. However, none of the cited gap-fill materials are disclosed in the cited references or in other related references known to the Examiner. The specific gap-fill material limitation, coupled with the other limitations of Claim 21, set Claim 21 and dependents clear of the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL G MILLER whose telephone number is (571)270-1861. The examiner can normally be reached M-F 9:00-5:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL G MILLER/ Primary Examiner, Art Unit 1712
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