DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I drawn to claims 12-20 in the reply filed on 08/17/2026 is acknowledged. Claims 1-11 are directed to non-elected group thereby withdrawn. Currently claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 12, line 11 recites “a plurality of third LDD regions having the third conductivity type”. However, the specification stated, “third LDD regions 44 having the second conductivity type.” and does not define “a third conductivity type” in the specification or in the claim.
Claims 13-20 inherit the deficiencies of the independent claim 12.
Appropriate corrections are required.
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12, line 11 recites “a plurality of third LDD regions having the third conductivity type”, without mentioning “a third conductivity type” earlier in the claim. There is insufficient antecedent basis for these limitations in the claim. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “the second conductivity type”.
Claim 13 line 1 recited “the dopant concentration of the second LDD region” without mentioning “a dopant concentration of the second LDD region” earlier in the claim or in the independent claim it depends on. Claim 12 upon which claim 13 depends, recited the plurality “a dopant concentration of the second LDD regions”. There is insufficient antecedent basis for these limitations in the claim. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “the dopant concentration of the second LDD regions”.
Claim 14 lines 2-3 and 5 recited “the same dopant concentration” without mentioning “a same dopant concentration” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 12 upon which claim 14 depends, does not recite “a same dopant concentration”. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “a same dopant concentration”.
Claim 16 line 1 recited “the metal silicide layers” without mentioning “a metal silicide layers” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 15 upon which claim 16 depends, recited “a plurality of metal silicide layers”. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “the plurality of metal silicide layers”.
Claim 17 line 1 recited “the metal silicide layers” without mentioning “a metal silicide layers” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 15 upon which claim 17 depends, recited “a plurality of metal silicide layers”. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “the plurality of metal silicide layers”.
Claim 18 lines 3-4 recited “the spacers” without mentioning “spacers” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 18 upon which claim 17 depends, and claim 15 upon which claim 17 depends, did not recite “spacers”. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “spacers”.
Claim 20 lines 3-4 recited “the spacers” without mentioning “spacers” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 19 upon which claim 20 depends, and claim 15 upon which claim 19 depends, did not recite “spacers”. Therefore, it is unclear, and the scope of the claim is unclear. For examination purposes, this will be interpreted as “spacers”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US 6084283 A) “Arai et al.”.
With Regard to Independent Claim 12, Arai et al. Figs. 1, 4 and 5 disclose an integrated circuit device, comprising:
a first gate structure (“a gate electrode and wiring pattern 105.” Column 8, Lines 57-58) of a medium voltage device having a first conductivity type (“P-channel MOSFETs” Column 8, Line 41), a second gate structure (“a gate electrode and wiring pattern 105.” Column 8, Lines 57-58; “N-well layers 102 for arranging P-channel MOSFETs, i.e., PMOSFETs, in a P-semiconductor substrate, i.e., a silicon substrate 101, are formed in both a high-breakdown-voltage-element area HBA and a low-breakdown-voltage-element area LBA.” Column 8, Lines 41-45), of a high voltage device having the first conductivity type, a third gate structure (Gate electrode 105 in the LBA formed on gate oxide 104 directly on P-sub 101) of a medium voltage device having a second conductivity type (“NMOSFET” Column 9, Lines 9-10), and a fourth gate structure (Gate electrode 105 in the HBA over P-sub 101) of a high voltage device having the second conductivity type (“high-breakdown-voltage NMOSFET” Column 8, Lines 61-62), respectively disposed in a first region (the active region of N-well 102 in the LBA in Fig. 4B), a second region (the active region of N-well 102 in the HBA in Fig. 4B), a third region (the active region of P-type substrate 101 in the LBA in Fig. 4B) and a fourth region (the active region of P-type substrate 101 in the HBA in Fig. 4B) of a substrate (“a silicon substrate 101” Column 8, Lines 43);
a plurality of first LDD regions having the first conductivity type (“an P.sup.- -LDD layer 118 of a middle concentration” Column 10, Lines 4-5), disposed in the first region and the second region (Fig. 4B shows 118 disposed in the first and second region);
a plurality of second LDD regions having the second conductivity type (“an N.sup.- -LDD layer 115 of a middle concentration” Column 10, Lines 1-2), disposed in the third region (Fig. 4B shows 115 disposed in the third region); and
a plurality of third LDD regions having the second conductivity type (“an N.sup.-- -LDD layer 116” Column 10, Line 1), disposed in the fourth region (Fig. 4B shows 116 disposed in the fourth region),
wherein a dopant concentration (“The N.sup.- -LDD layer 115 and the P.sup.- -LDD layer 118 have a concentration of the order of 10.sup.20 /cm.sup.3” Column 10, Lines 62-63) of the second LDD regions 115 is greater (“The impurity concentration of the N.sup.-- -LDD portion of the high-breakdown-voltage NMOSFET is set to be lower than that of the N.sup.- -LDD portion of the low-breakdown-voltage NMOSFET.” Column 2 Lines 37-41) than a dopant concentration ( “The N.sup.-- -LDD layer 116 and the P.sup.-- -LDD layer 119 have a concentration of the order of 10.sup.19 /cm.sup.3” Column 10 Lines 63-65) of the third LDD regions 116.
With Regard to Claim 14, Arai et al. discloses the limitations of claim 12. Arai et al. further discloses further comprising:
a plurality of first heavily doped regions having the first conductivity type, with the same dopant concentration, disposed in the substrate in the first region and the second region (“a P.sup.+ -diffusion layer 117 of a high concentration” Column 10 Lines 3); and
a plurality of second heavily doped regions having the second conductivity type, with the same dopant concentration, disposed in the substrate in the third region and the fourth region (“an N.sup.+ -diffusion layer 114 of a high concentration,” Column 9, Lines 66-67).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over (US 6084283 A) “Arai et al.”.
With Regard to Claim 13, Arai et al. discloses the limitations of claim 12. Arai et al. further discloses wherein: the dopant concentration of the second LDD region 115 and a dopant concentration of the first LDD regions 118 (“The N.sup.- -LDD layer 115 and the P.sup.- -LDD layer 118 have a concentration of the order of 10.sup.20 /cm.sup.3” Column 10, Lines 62-63).
However, Arai et al. does not explicitly disclose the dopant concentration of the second LDD region 115 is greater than a dopant concentration of the first LDD regions 118.
However, in the disclosure of Arai et al. discloses a decrease in the impurity concentration in an LDD portion directly increases its parasitic resistance and lowers the channel current Id (Column 2 Lines 6-8) and phosphorous ions are implanted into the substrate 101 at an acceleration energy of 45 KeV and a dose of 1.times.10.sup.14 /cm.sup.2. As a result, a structure shown in FIG. 1B is obtained (Column 12, Lines 27-29), and a resist pattern 109 is formed to cover at least positions corresponding to the NMOSFETs. Then, using the resist pattern 109 as a mask, boron ions are implanted into the substrate 101 at an acceleration energy of 20 KeV and a dose of 1.times.10.sup.13 /cm.sup.2 (FIG. 3A) (Column 9, Lines 22-28).
MPEP 2144.05(II)(A) states “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.)”
It would have been obvious to person having ordinary skill in the art before the effective filling date to optimize the concentrations of LDD 115 and LDD 118 of Arai et al. because, as is clear from FIGS. 10A and 10B which show dependency of the breakdown voltage BV and electric current (transistor-channel current) Id on LDD concentration in N-channel MOSFETs, the impurity concentration of an LDD portion has a great influence on the transistor-channel current Id (Column 2 Lines 1-5).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over (US 6084283 A) “Arai et al.” in view of Chang; Wei-Hsuan (US 20230261092 A1) “Chang et al.” further in view of Wu; Hsin-Han (US 20230307524 A1) “Wu et al.”.
With Regard to Claim 15, Arai et al. discloses the limitations of claim 14. However, Arai et al. does not disclose, further comprising:
a plurality of metal silicide layers, disposed on the plurality of first LDD regions in the first region and the second region, on the plurality of second LDD regions in the third region and on the plurality of third LDD regions in the fourth region.
In the similar field of endeavor of semiconductor devices, Chang et al. Figs. 1-4 discloses a plurality of metal silicide layers (“silicide layers 24” ¶ [0016]), disposed on the plurality of first LDD regions in the first region and the second region, on the plurality of second LDD regions in the third region and on the plurality of third LDD regions in the fourth region (Fig. 4 shows 24 covers S/D regions, LDD1 and LDD2 regions).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. so that current leakage can be effectively prevented (Chang et al. ¶ [0021]).
With Regard to Claim 16, Arai et al. as modified by Chang et al. discloses the limitations of claim 15. Arai et al. further discloses, wherein:
spacers on sidewalls (“a silicon oxide film to be used as a side wall material and having a thickness of about 150 nm is formed by means of a conventional LP-CVD technique. Then, the silicon oxide film is etched back to form side walls 110 by means of an anisotropic etching technique.” Column 9 Line 28-34) of the first gate structure in the first region;
However, Arai et al. does not discloses, the metal silicide layers are in contact with spacers on sidewalls of the first gate structure in the first region; distances between the metal silicide layers and spacers on sidewalls of the second gate structure are different in the second region; the metal silicide layers are in contact with spacers on sidewalls of the third gate structure in the third region; and distances between the metal silicide layers and spacers on sidewalls of the fourth gate structure are different in the fourth region.
In the similar field of endeavor of semiconductor devices, Chang et al. Figs. 1-4 discloses the metal silicide layers are in contact with spacers on sidewalls of the first gate structure in the first region (“The silicide layers 24 are not only formed directly on the source/drain doping regions S/D, but also fills into the recess 22. That is, the silicide layers 24 will exceed the region directly on the source/drain doping regions S/D. Now, the middle voltage transistor 100 of the present invention is completed. The fabricating process of the middle voltage transistor 100 is suitable for manufacturing N-type transistors and P-type transistors.” ¶ [0016]; therefore, it will be in contact with the gate structure of Arai et al.); the metal silicide layers are in contact with spacers on sidewalls of the third gate structure in the third region (“The silicide layers 24 are not only formed directly on the source/drain doping regions S/D, but also fills into the recess 22. That is, the silicide layers 24 will exceed the region directly on the source/drain doping regions S/D. Now, the middle voltage transistor 100 of the present invention is completed. The fabricating process of the middle voltage transistor 100 is suitable for manufacturing N-type transistors and P-type transistors.” ¶ [0016]; therefore, it will be in contact with the gate structure of Arai et al.).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. so that current leakage can be effectively prevented (Chang et al. ¶ [0021]).
However, Chang et al. does not disclose, distances between the metal silicide layers and spacers on sidewalls of the second gate structure are different in the second region; and distances between the metal silicide layers and spacers on sidewalls of the fourth gate structure are different in the fourth region.
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 9-14 discloses distances between the metal silicide layers 54A and spacers SP1 and SP2 on sidewalls of the second gate structure 60 are different in the second region; and distances between the metal silicide layers 54A and spacers SP1 and SP2 on sidewalls of the fourth gate structure 60 are different in the fourth region (“the high voltage semiconductor device 101 may further include a source/drain doped region 52A and a silicide layer 54A, the source/drain doped region may be disposed in the first drift region 12A, and the silicide layer 54A may be disposed in the source/drain doped region 52A and/or disposed on the source/drain doped region 52A. The sub gate structure 60A may be located between the gate structure 60G and the source/drain doped region 52A in the first direction D1, and the sub gate structure 60A may be electrically separated from the gate structure 60G and the source/drain doped region 52A. The distance between the gate structure 60G and the source/drain doped region 52A and/or the distance between the gate structure 60G and the silicide layer 54A may be increased by the disposition of the sub gate structure 60A, and the electrically conductive silicide layer may be kept from being formed on the first drift region 12A located between the spacer structure SP1 and the spacer structure SP2 and/or the first drift region 12A located between the gate structure 60G and the sub gate structure 60A by the disposition of the first insulation structure BS1.” ¶ [0033]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. with the spacer arrangement of Wu et al. so that the electrical performance of the high voltage semiconductor device 101 may be improved (Wu et al. ¶ [0033]).
With Regard to Claim 17, Arai et al. as modified by Chang et al. discloses the limitations of claim 15. Arai et al. further discloses, spacers (“a silicon oxide film to be used as a side wall material and having a thickness of about 150 nm is formed by means of a conventional LP-CVD technique. Then, the silicon oxide film is etched back to form side walls 110 by means of an anisotropic etching technique.” Column 9 Line 28-34)
However, Arai et al. does not disclose, wherein a distance between one of the metal silicide layers and the second gate structure in the second region is greater than a distance between the metal silicide layer and the first gate structure in the first region; and
a distance between one of the metal silicide layers and the fourth gate structure in the fourth region is greater than a distance between the metal silicide layer and the third gate structure in the third region.
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 9-14 discloses wherein a distance between one of the metal silicide layers 54A/54B and the second gate structure 60A/60B in the second region is greater than a distance between the metal silicide layer 54A/54B and the first gate structure 60A/60B in the first region; and a distance between one of the metal silicide layers and the fourth gate structure in the fourth region is greater than a distance between the metal silicide layer and the third gate structure in the third region (“the high voltage semiconductor device 101 may further include a source/drain doped region 52A and a silicide layer 54A, the source/drain doped region may be disposed in the first drift region 12A, and the silicide layer 54A may be disposed in the source/drain doped region 52A and/or disposed on the source/drain doped region 52A. The sub gate structure 60A may be located between the gate structure 60G and the source/drain doped region 52A in the first direction D1, and the sub gate structure 60A may be electrically separated from the gate structure 60G and the source/drain doped region 52A. The distance between the gate structure 60G and the source/drain doped region 52A and/or the distance between the gate structure 60G and the silicide layer 54A may be increased by the disposition of the sub gate structure 60A, and the electrically conductive silicide layer may be kept from being formed on the first drift region 12A located between the spacer structure SP1 and the spacer structure SP2 and/or the first drift region 12A located between the gate structure 60G and the sub gate structure 60A by the disposition of the first insulation structure BS1.” ¶ [0033]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. with the spacer arrangement of Wu et al. so that the electrical performance of the high voltage semiconductor device 101 may be improved (Wu et al. ¶ [0033]).
With Regard to Claim 18, Arai et al. as modified by Chang et al. and Wu et al. discloses the limitations of claim 17. Arai et al. further discloses, the first gate structure, the second gate structure, the third gate structure, the fourth gate structure as shown in claim 12, and the spacers (“a silicon oxide film to be used as a side wall material and having a thickness of about 150 nm is formed by means of a conventional LP-CVD technique. Then, the silicon oxide film is etched back to form side walls 110 by means of an anisotropic etching technique.” Column 9 Line 28-34)
However, Arai et al. does not disclose further comprising: a stop layer, disposed on the substrate, wherein the stop layer covers the gate structure, and the metal silicide layers, and covers a top surface of one of the first LDD regions and a top surface of one of the first heavily doped regions in the second region, and a top surface of one of the third LDD regions and a top surface of one of the second heavily doped regions in the fourth region
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 9-14 discloses further comprising: a stop layer (“an insulation layer 56, a dielectric layer 62” ¶ [0037]), disposed on the substrate (“ substrate 10” ¶ [0038]), wherein the stop layer 62 covers the gate structure 60, and the metal silicide layers, and covers a top surface of one of the first LDD regions and a top surface of one of the first heavily doped regions in the second region, and a top surface of one of the third LDD regions and a top surface of one of the second heavily doped regions in the fourth region (“the first drift region 12A and the second drift region 12B may include doped regions formed by performing a doping process (such as an implantation process) to the semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor substrate with a first conductivity type or include a first conductivity type region (such as a doped well region with the first conductive type, not illustrated), the first drift region 12A and the second drift region 12B may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type, but not limited thereto. In some embodiments, the source/drain region 52A and the source/drain region 52B may include doped regions formed in the semiconductor substrate 10 by a doping process (such as an implantation process). In some embodiments, the conductivity type of the source/drain region 52A and the source/drain region 52B may be identical to the conductivity type of the first drift region 12A and the second drift region 12B, but the dopant concentration of the source/drain region 52A and the source/drain region 52B may be higher than that of the first drift region 12A and the second drift region 12B. For example, the source/drain region 52A and the source/drain region 52B may be n-type heavily doped regions, but not limited thereto.” ¶ [0038]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. with the spacer arrangement of Wu et al. so that the electrical performance of the high voltage semiconductor device 101 may be improved (Wu et al. ¶ [0033]).
With Regard to Claim 19, Arai et al. as modified by Chang et al. discloses the limitations of claim 15. Arai et al. further discloses, wherein:
the metal silicide layers are in contact with spacers on sidewalls of the first gate structure in the first region;
distances between the metal silicide layers and spacers on sidewalls of the second gate structure in the second region are different;
the metal silicide layers are in contact with spacers on sidewalls of the third gate structure in the third region; and
distances between the metal silicide layers and spacers on sidewalls of the fourth gate structure in the fourth region are the same.
Arai et al. as modified by Chang et al. discloses the limitations of claim 15. Arai et al. further discloses, wherein:
spacers on sidewalls (“a silicon oxide film to be used as a side wall material and having a thickness of about 150 nm is formed by means of a conventional LP-CVD technique. Then, the silicon oxide film is etched back to form side walls 110 by means of an anisotropic etching technique.” Column 9 Line 28-34) of the first gate structure in the first region;
However, Arai et al. does not discloses, the metal silicide layers are in contact with spacers on sidewalls of the first gate structure in the first region; distances between the metal silicide layers and spacers on sidewalls of the second gate structure in the second region are different; the metal silicide layers are in contact with spacers on sidewalls of the third gate structure in the third region; and distances between the metal silicide layers and spacers on sidewalls of the fourth gate structure in the fourth region are same.
In the similar field of endeavor of semiconductor devices, Chang et al. Figs. 1-4 discloses the metal silicide layers are in contact with spacers on sidewalls of the first gate structure in the first region (“The silicide layers 24 are not only formed directly on the source/drain doping regions S/D, but also fills into the recess 22. That is, the silicide layers 24 will exceed the region directly on the source/drain doping regions S/D. Now, the middle voltage transistor 100 of the present invention is completed. The fabricating process of the middle voltage transistor 100 is suitable for manufacturing N-type transistors and P-type transistors.” ¶ [0016]; therefore, it will be in contact with the gate structure of Arai et al.); the metal silicide layers are in contact with spacers on sidewalls of the third gate structure in the third region (“The silicide layers 24 are not only formed directly on the source/drain doping regions S/D, but also fills into the recess 22. That is, the silicide layers 24 will exceed the region directly on the source/drain doping regions S/D. Now, the middle voltage transistor 100 of the present invention is completed. The fabricating process of the middle voltage transistor 100 is suitable for manufacturing N-type transistors and P-type transistors.” ¶ [0016]; therefore, it will be in contact with the gate structure of Arai et al.).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. so that current leakage can be effectively prevented (Chang et al. ¶ [0021]).
However, Chang et al. does not disclose, distances between the metal silicide layers and spacers on sidewalls of the second gate structure in the second region are different; and distances between the metal silicide layers and spacers on sidewalls of the fourth gate structure in the fourth region are same.
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 1-15 discloses distances between the metal silicide layers 54A and spacers SP1 and SP2 on sidewalls of the second gate structure 60 in the second region are different (“the high voltage semiconductor device 101 may further include a source/drain doped region 52A and a silicide layer 54A, the source/drain doped region may be disposed in the first drift region 12A, and the silicide layer 54A may be disposed in the source/drain doped region 52A and/or disposed on the source/drain doped region 52A. The sub gate structure 60A may be located between the gate structure 60G and the source/drain doped region 52A in the first direction D1, and the sub gate structure 60A may be electrically separated from the gate structure 60G and the source/drain doped region 52A. The distance between the gate structure 60G and the source/drain doped region 52A and/or the distance between the gate structure 60G and the silicide layer 54A may be increased by the disposition of the sub gate structure 60A, and the electrically conductive silicide layer may be kept from being formed on the first drift region 12A located between the spacer structure SP1 and the spacer structure SP2 and/or the first drift region 12A located between the gate structure 60G and the sub gate structure 60A by the disposition of the first insulation structure BS1.” ¶ [0033])
and distances between the metal silicide layers 54A and spacers SP1 on sidewalls of the fourth gate structure 60 in the fourth region are same (“the distance between the source/drain doped region and the spacer structure SP1 may be controlled by adjusting the condition of the patterned mask layer covering the first drift region 12A and the second drift region 12B.” ¶ [0060]; therefore, the same distance can be achieved).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. with the spacer arrangement of Wu et al. so that the electrical performance of the high voltage semiconductor device 101 may be improved (Wu et al. ¶ [0033]).
With Regard to Claim 20, Arai et al. as modified by Chang et al. and Wu et al. discloses the limitations of claim 19. Arai et al. further discloses, the first gate structure, the second gate structure, the third gate structure, the fourth gate structure as shown in claim 12, and the spacers (“a silicon oxide film to be used as a side wall material and having a thickness of about 150 nm is formed by means of a conventional LP-CVD technique. Then, the silicon oxide film is etched back to form side walls 110 by means of an anisotropic etching technique.” Column 9 Line 28-34)
However, Arai et al. does not disclose further comprising: a stop layer, disposed on the substrate, wherein the stop layer covers the gate structure, and the metal silicide layers, and covers a top surface of one of the first LDD regions and top surfaces of the first heavily doped regions in the second region, and top surfaces of the third LDD regions and a top surface of one of the second heavily doped regions in the fourth region
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 9-14 discloses further comprising: a stop layer (“an insulation layer 56, a dielectric layer 62” ¶ [0037]), disposed on the substrate (“ substrate 10” ¶ [0038]), wherein the stop layer 62 covers the gate structure 60, and the metal silicide layers, and covers top surfaces of the first LDD regions and a top surface of one of the first heavily doped regions in the second region, and a top surface of one of the third LDD regions and top surfaces of the second heavily doped regions in the fourth region (“the first drift region 12A and the second drift region 12B may include doped regions formed by performing a doping process (such as an implantation process) to the semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor substrate with a first conductivity type or include a first conductivity type region (such as a doped well region with the first conductive type, not illustrated), the first drift region 12A and the second drift region 12B may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type, but not limited thereto. In some embodiments, the source/drain region 52A and the source/drain region 52B may include doped regions formed in the semiconductor substrate 10 by a doping process (such as an implantation process). In some embodiments, the conductivity type of the source/drain region 52A and the source/drain region 52B may be identical to the conductivity type of the first drift region 12A and the second drift region 12B, but the dopant concentration of the source/drain region 52A and the source/drain region 52B may be higher than that of the first drift region 12A and the second drift region 12B. For example, the source/drain region 52A and the source/drain region 52B may be n-type heavily doped regions, but not limited thereto.” ¶ [0038]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Arai et al. including the silicide layers of Chang et al. with the spacer arrangement of Wu et al. so that the electrical performance of the high voltage semiconductor device 101 may be improved (Wu et al. ¶ [0033]).
Conclusion
The Prior art (US 5917218 A) “Choi et al.” filing date 1997-02-21; (US 20200105941 A1) “DUTTA” and (US 6455386 B1) “Mirabel” filing date 1999-06-02, made of record and not relied upon is considered pertinent to applicant’s disclosure.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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