CTNF 18/415,668 CTNF 83806 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Election/Restrictions Applicant's election with traverse of Invention I and Species A (Claims 1-15, Figs. 1A-1H) in the reply filed on 04/24/2026 is acknowledged. The traversal is on the ground(s) that: The restricted of species of Figs. 1A-1H and Figs. 2A-2E were not shown that they are independent or distinct. Examiner agreed that Figs. 1A-1H and Figs. 2A-2E are not patentably distinct species. However, the requirement is still deemed proper and is therefore made FINAL. 08-05 AIA Claim s 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention/species , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/24/2026 . Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 01/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 3 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hlad et al. (US 2012/0161330) in view of Lin et al. (US 2016/0118355) . As for claims 1 and 3, Hlad et al. disclose in Figs. 1-7 and the related text a method of forming a semiconductor package, comprising: providing a semiconductor die 502, wherein the semiconductor die comprises die connectors 503/504 protruding from a first (lower) side of the semiconductor die (Fig. 6-7, [0046]); forming a layer (around 503/504, fig. 6-7) on the first side of the semiconductor die (Fig. 6-7), the layer covering (portion of) the die connectors 503/504; bonding the die connectors 503/504 of the semiconductor die 502 to interposer connectors 215/233/245 of an interposer structure 101; and forming an underfill layer 650 around (a portion of) the interposer connectors (Fig. 7, [0048]). Hlad et al. do not teach the layer comprise polymer and step of planarizing the polymer layer until surfaces of the die connectors are exposed, wherein after planarizing the polymer layer, a surface of the polymer layer is flushed with exposed surfaces of the die connectors. Lin et al. teach in Figs. 5e5f and the related text a polymer layer 564/164 [0072] covering connector 170, and planarizing the polymer layer until surfaces of the connector are exposed ([0066]-[0067]), wherein after planarizing the polymer layer 564/164, a surface of the polymer layer is flushed with exposed surfaces of the connector 170 (Fig. 6-7). Hlad et al. and Lin et al. are analogous art because they both are directed interconnections and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hlad et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Hlad et al. to include the limitations as taught by Lin et al., in order to provide suitable material and techniques (Lin et al. [0067]). As for claim 6, Hlad et al. in view of Lin et al. disclose the method of claim 1, Hlad further disclose the die connectors comprise first die connectors having a first width and second die connectors having a second width different from the first width (Fig. 6-7). As for claim 7, Hlad et al. in view of Lin et al. disclose the method of claim 1, Hlad further disclose the die connectors comprise die pads 503 and die bumps 504, the interposer connectors comprise interposer pads 245 and interposer bumps 233, and a shape of the die bumps is different from a shape of the interposer bumps (Fig. 6-7) . 07-21-aia AIA Claim s 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hlad in view of Lin et al. further in view Yew et al. (US 2022/0230990) . As for claims 2 and 8, Hlad et al. in view of Lin et al. disclose the method of claim 1, except the underfill layer further creeps onto a sidewall of the polymer layer; and forming a board substrate 202 below and electrically connected to the interposer structure. Yew et al. teach in Fig. 1A-2E and the related text an underfill layer 130 further creeps onto a sidewall of a polymer layer 42 [0020]; and forming a board substrate below and electrically connected to the interposer structure 110 (fig. 2a-2e). Hlad et al., Lin et al. and Yew et al. are analogous art because they both are directed interconnections and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hlad et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Hlad et al. to include the limitations as taught by Yew et al., in order to improve mechanical strength and to support the packaging device . 07-21-aia AIA Claim s 9 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0091131) in view of Chen et al. (US 2021/0066263) . As for claim 9, Kim et al. disclose in Figs. 1-6 and the related text a method of forming a semiconductor package, comprising: forming first die pads (right 230) and second die pads (left 230) on a first side of a semiconductor die 200; forming first die bumps (right 310) on the first die pads and forming second die bumps (left 310) on the second die pads (Fig. 1-5); forming a polymer layer 232 [0044] on/over the first side of the semiconductor die 200 and covering/aside the first die pads, the second die pads, the first die bumps and the second die bumps (Figs. 1/5); and bonding the semiconductor die 200 to an interposer structure 100 through the first die bumps and the second die bumps (Fig. 1/5). Kim et al. do not disclose partially removing the first die pads and the second die pads. Chen et al. teach in Fig. 4 or 6A and the related text partially removing the first die pads and the second die pads 117A’ [0053]. Kim et al. and Chen et al. are analogous art because they both are directed interconnections and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include a step of partially removing the first die pads and the second die pads as taught by Chen et al, in order to reduce thickness. As for claim 13, Kim et al. disclose the method of claim 9, wherein (a portion of) the first die pads having a first width and (an entire of) the second die pads having a second width different from the first width (fig. 1/5). As for claim 14, Kim et al. disclose the method of claim 9, wherein (a portion of) the first die bumps having a first width and (an entire of) the second die bumps having a second width different from the first width (Fig. 1/5). As for claim 15, Kim et al. disclose the method of claim 9, further comprising forming an underfill layer 400 in a space between the semiconductor die 200 and the interposer structure 100 (Fig. 1/5 [0048]) . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Chen et al. and further in view of Matsunaga et al. (US 2003/0178227) . 12. (Original)The method of claim 9, wherein partially removing the first die pads and the second die pads comprises trimming the first die pads and the second die pads. Matsunaga et al. teach in Figs. 11-12B, [0042] and the related text trimming method can be used to partially remove a method layer 22. Kim et al., Chen et al. and Matsunaga et al. are analogous art because they both are directed interconnections and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to use trimming process as taught by Matsunaga et al. to provide excellent in fine processing (Matsunaga et al. [0042]) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 4-5 and 10-11 are allowed. The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious “a method of forming the die connectors of the semiconductor die comprises: forming a seed layer on the first side of the semiconductor die; forming a photoresist layer with opening patterns on the seed layer; plating a first metal layer, a second metal layer, a third metal layer and a solder layer sequentially in the opening patterns; removing the photoresist layer; and partially removing the seed layer, the first metal layer and the third metal layer” as recited in claim 4 and “a method of forming the polymer layer comprises: forming a polymer material on the first side of the semiconductor die, the polymer material covering the first die pads, the second die pads, the first die bumps and the second die bumps; and performing a polishing process to the polymer layer and the first die bumps and the second die bumps”, as recited in claim 10. Claims 5 and 11 depend among objected claims 4 and 10. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811 Application/Control Number: 18/415,668 Page 2 Art Unit: 2811 Application/Control Number: 18/415,668 Page 3 Art Unit: 2811 Application/Control Number: 18/415,668 Page 4 Art Unit: 2811 Application/Control Number: 18/415,668 Page 5 Art Unit: 2811 Application/Control Number: 18/415,668 Page 6 Art Unit: 2811 Application/Control Number: 18/415,668 Page 7 Art Unit: 2811 Application/Control Number: 18/415,668 Page 8 Art Unit: 2811
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