DETAILED ACTION
This action is responsive to the application No. 18/415,955 filed on January 18, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, and Species IIB, corresponding to device claims 1-15, in the reply filed on May 5, 2026, is acknowledged. Claims 16-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 8 recites a vertical thickness of the active semiconductor layer is non-uniform. This limitation includes an infinite number of non-uniform layers, e.g. as shown below, none of which are disclosed.
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The active layer apparently has a different, uniform thickness, in each region. There is no written description support for all of the possible non-uniform thickness layers as this includes layers not disclosed or contemplated by Applicant (see examples above).
The limitation should more accurately recite: a vertical thickness of the active layer in the first active region is different than a vertical thickness of the active layer in the second active region.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites a vertical thickness of the active semiconductor layer is non-uniform. The claimed non-uniform thickness is confusing in view of the figures and specification which appear to show the active layer has a uniform thickness in each active region. The active layer simply has a different, uniform thickness, in each region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2013/0126976).
(Re Claim 1) Yu teaches a structure, comprising (Fig. 5B):
an insulator (25) within a substrate, wherein the substrate includes a first active region (10) adjacent a first sidewall of the insulator and a second active region (5) adjacent a second sidewall of the insulator opposite the first sidewall;
a conductive bridge (35 and/or 30) over the insulator and coupling the first active region to the second active region of the substrate;
a gate dielectric layer (4 and/or the ILD 80 is formed in, not shown, ¶54) over the conductive bridge;
a first work function metal (20, ¶¶24-27) over the first active region; and
a second work function metal (15) over the second active region.
(Re Claim 2) wherein an upper surface of the insulator is above the substrate (Fig. 5B).
(Re Claim 6) wherein the first work function metal has a greater work function than a work function of the second work function metal (the p-type work function metals, Ru, Pt, Mo, etc. have a greater work function than the n-type work function metals disclosed, TiN, HfN, HfSi).
(Re Claim 7) Yu teaches a structure, comprising:
a semiconductor-on-insulator stack (SOI stack) including a semiconductor layer, a buried insulator over the semiconductor layer, and an active semiconductor layer over the buried insulator (SOI substrate, ¶18);
a first insulator (25) within the SOI stack, wherein the SOI stack includes a first active region (10) adjacent a first sidewall of the first insulator and a second active region (5) adjacent a second sidewall of the first insulator opposite the first sidewall, wherein an upper surface of the first insulator is above the active semiconductor layer (Fig. 5B);
a first conductive bridge (35 and/or 30) over the first insulator and coupling the first active region of the active semiconductor layer to the second active region of the active semiconductor layer;
a gate dielectric layer over the first conductive bridge (4 and/or the ILD 80 is formed in, not shown, ¶54);
a first work function metal (20, ¶¶24-27) over the first active region; and
a second work function metal (15) over the second active region.
(Re Claim 12) wherein the first conductive bridge is under the first work function metal and the second conductive bridge is beneath the second work function metal (Fig. 5B, under/beneath are arbitrary since the figures/device may be rotated and no directions are defined).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. as applied above and below regarding claim 10, and further in view of Chen et al. (US 2005/0242398) and Lian (US 2014/0339645).
(Re Claims 3 and 11) wherein a vertical thickness of the gate dielectric layer is non-uniform.
(Re Claim 4) wherein a first vertical thickness of the gate dielectric layer above the first active region is less than a second vertical thickness of the gate dielectric layer above the second active region.
Yu is silent regarding a non-uniform gate dielectric thickness and that the gate dielectric in the first active region is less than the thickness of the gate dielectric in the second active region. A PHOSITA desiring to make, use, and improve upon Yu’s device would be motivated to look to related art to teach related devices for potential improvements. Related art from Chen teaches a non-uniform gate dielectric, having a different thickness in two different active regions is advantageous for tuning the threshold voltage. The thicker gate dielectric 224 enables a higher threshold voltage, while the thinner gate dielectric corresponds to a lower threshold voltage (¶42-44, Figs. 3b-3h). Related art from Lian also teaches forming gate dielectrics having different thicknesses over different active regions (Fig. 3I). Liam recognizes this as common in modern devices due to different voltage requirements for different transistors in a device, devices requiring higher voltages require thicker gate insulation, while lower voltages require thinner insulation (¶9). In view of Chen and Liam, a PHOSITA would find it obvious to use a thicker and thinner gate dielectrics over the active regions of Yu to enable fabrication of transistors with different threshold voltages in the same IC device, thicker dielectrics wherever a higher voltage is required and a thinner gate dielectrics where lower voltages are required to enable multi-threshold transistors operating at different voltages.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. as applied above and below regarding claim 10, and further in view of Long et al. (US 2001/0017390).
(Re Claim 5) wherein the first work function metal abuts the second work function metal over one of the first active region and the conductive bridge.
(Re Claim 14) wherein the first work function metal abuts the second work function metal over one of the first active region and the intermediate active region.
Yu is silent regarding the work function metals abutting each other over the active region, and/or similarly over the intermediate active region (re claim 10). A PHOSITA desiring to make, use, and improve upon Yu’s device would be motivated to look to related art to teach related devices for potential improvements. Related art from Long teaches forming a transistor having two different work function metals, GM1 and GM2, abutting each other over the active region (Figs. 2-3e). Long teaches that short‑channel effects can be suppressed by engineering the vertical electric field along the channel using non‑uniform gate dielectrics and by “strategically placing the same or different gate materials above various gate dielectric materials” to further tailor the device performance (¶¶6-7,79). In view of this, it would have been obvious to PHOSITA to form a transistor gate comprising two abutting metals of different work functions, thereby locally adjusting threshold and gate‑to‑drain/source coupling along the channel to achieve the known benefits of improved short‑channel control and capacitance distribution.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. as applied above, and further in view of Winstead et al. (US 2008/0111153).
(Re Claim 8) wherein a vertical thickness of the active semiconductor layer is non-uniform.
Yu is silent regarding vertical thickness of the active semiconductor layer is non-uniform. A PHOSITA desiring to make, use, and improve upon Yu’s device would be motivated to look to related art to teach related devices for potential improvements. Related art from Winstead teaches forming active regions having different thicknesses (Figs. 1-7: regions 24 and 26 and regions 64 and 66). Winstead teaches (see abstract, ¶¶5-9, 20-22, 43-52, 63) that localized thickness and heterojunction engineering in the active region allows p‑channel and n‑channel transistors on the same substrate to have substantially matched subthreshold carrier depths and switching behavior, improving overall CMOS performance. For these advantages, a PHOSITA would find it obvious to similarly form the active regions having different thicknesses, resulting from the additional epitaxial material 32/62 to form the heterojunction in Yu’s device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al.
(Re Claim 10) further comprising: a second insulator adjacent the first insulator;
a second conductive bridge over the second insulator; and an intermediate active region of the active semiconductor layer adjacent the second insulator.
Yu is silent regarding a second insulator adjacent the first insulator, a second conductive bridge over the second insulator, and an intermediate active region of the active semiconductor layer adjacent the second insulator. A PHOSITA would recognize that Yu only teaches a small representative region of larger device area (Fig. 5a), and that the device regions 5 and 10 may obviously extend beyond the figure to include many more PMOS and NMOS transistors in an array1, semiconductor devices conventionally form arrays of NMOS/PMOS transistors to form complex circuits. When these are repeated in a larger array, e.g. the section shown in Fig. 5b, there will be a second insulator adjacent the first insulator, a second conductive bridge over the second insulator, and an intermediate active region of the active semiconductor layer adjacent the second insulator, the mapping repeating for each additional insulator and active region.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. as applied above, and further in view of Daval et al. (US 2012/0228689).
(Re Claim 13) further comprising:
a first back biasing region within the semiconductor layer below the first work function metal;
a second back biasing region within the semiconductor layer below the second work function metal; and
an intermediate back biasing region within the semiconductor layer and horizontally between first back biasing region and the second back biasing region.
Yu is silent regarding the back biasing regions, although Yu teaches the NMOS/PMOS devices are formed on an SOI substrate. A PHOSITA would recognize back biasing is conventional in many CMOS/SOI architectures. In SOI CMOS, back biasing through semiconductor regions beneath the buried oxide (acting as a back-gate) is well known for dynamically modulating the threshold voltage, controlling leakage current, and improving device speed. Related art from Daval discloses (Fig. 2, ¶¶2-27, and claims 9-12, 18, and 20) back biasing though layers 7 and 6, below each and between, the two active regions. A PHOSITA would find this obvious to include in Yu’s SOI substrate below and between the active regions to provide advantages of back-biasing as noted above.
Claims 7, 9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhag et al. (US 2023/0112377) in view of Yu et al. (US 2013/0126976).
(Re Claim 7) Shanbhag teaches a structure, comprising (see Fig. 6 and supporting text):
a semiconductor-on-insulator stack (SOI stack) including a semiconductor layer, a buried insulator over the semiconductor layer, and an active semiconductor layer over the buried insulator (SOI substrate 12, ¶17);
a first insulator (20) within the SOI stack, wherein the SOI stack includes a first active region (18 on left) adjacent a first sidewall of the first insulator and a second active region (18 on right) adjacent a second sidewall of the first insulator opposite the first sidewall, wherein an upper surface of the first insulator is above the active semiconductor layer (Fig. 6);
a first conductive bridge (30) over the first insulator and coupling the first active region of the active semiconductor layer to the second active region of the active semiconductor layer;
a first work function metal (32a, ¶30) over the first active region; and
a second work function metal (the other 32a) over the second active region.
Shanbhag is silent regarding a gate dielectric layer over the first conductive bridge, although Shanbhag discloses (¶33): “Further back end of the line (BEOL) processes can be performed including metallization processes known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure.” A PHOSITA would understand this to include forming interconnects in ILD layers, noting the device in Fig. 6 lacks any means for making electrical connections to the transistors. Related art from Yu discloses after forming transistors, interconnects are formed in a dielectric layer (¶54). A PHOSITA would find this dielectric layer/metal interconnects obvious to include in Shanbhag’s device for the purpose of forming electrical connections to the device. The ILD layer meets the claimed dielectric layer over the insulating layer.
(Re Claim 9) wherein the first conductive bridge includes a doped semiconductor material (30 is doped, ¶32).
(Re Claim 15) wherein a vertical thickness of the active semiconductor layer (18) is less than a vertical thickness of the first conductive bridge (30, Fig. 6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art discloses devices with dual and multi-work function metal gates, active regions and gate dielectrics of different thicknesses, and related transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
1 regarding duplication of parts, also see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
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