DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicants’ election of invention I, drawn to claims 1-6 & 8-14; species I, drawn to Figures 2B, 7, and 8; and amended claims 21-26 are acknowledged. Claims 7 & 15-20, drawn to an unelected invention/species are thus withdrawn from further examination. Claims 1-6, 8-14, and 21-26 are examined herein.
In a telephonic conversation with attorney Rodger Knapp on 07/24/2026, clarification and confirmation was made of applicant’s election of species I, drawn to Figures 2B, 7, and 8 which appear drawn to the elected and amended claims 1-6, 8-14, and 21-26; rather than species II which is drawn to Figure 9 and the withdrawn claim 7.
Election/Restrictions
Claims 7 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/19/2026.
Applicant’s election without traverse of claims 1-6, 8-14 and amended claims 21-26 in the reply filed on 06/19/2026 are acknowledged.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-10, 21, and 24-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (US Patent No 10,312,201).
Regarding claim 1, Hu (US Patent No 10,312,201) teaches a method of manufacturing a semiconductor device (die package 613, Figure 14), the method comprising: receiving a first semiconductor device (die 512, Figure 14), the first semiconductor device comprising: a functional region (device area 518, Figure 14); and a seal ring region (inactive area 551, Figure 14), the seal ring region comprising a first seal ring (seal ring units 536, Figure 14); bonding the first semiconductor device to a semiconductor wafer (die 612, Figure 14, col 20 line 64 - col 21 line 3, teaches die is bonded to a similarly formed die, in accordance with some embodiments...Die and die may be bonded as a wafer-to-wafer, chip-to-chip, or chip-to-wafer process), the bonding comprising: bonding a first dielectric (bond dielectric layer 540, Figure 14) of the first semiconductor device to a second dielectric (bond dielectric layer 640, Figure 14) of the semiconductor wafer; bonding first bond pads (bond pads 542, Figure 14) within the functional region to second bond pads (bond pads 642, Figure 14) within the semiconductor wafer; and bonding the first seal ring to a first bond metal (ring-like bond pads 552 + bond pad vias 554, Figure 14) within the semiconductor wafer, as claimed.
Regarding claim 2, Hu (US Patent No 10,312,201) teaches the method of claim 1, as claimed. Hu (US Patent No 10,312,201) further teaches wherein the first seal ring fully surrounds the functional region (Figure 13c, col 20, lines 13-14 + 49-51, teaches An inactive zone is located at the periphery of die...inactive zone corresponds to the location of the seal ring unit), as claimed.
Regarding claim 8, Hu (US Patent No 10,312,201) teaches a method of manufacturing a semiconductor device (die package 613, Figure 14), the method comprising: receiving a semiconductor substrate (substrate 522, Figure 14, col 19 lines 50-51 + col 4 line 5-8, teaches die contains similar features and structures as dies...Die includes a substrate, which may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbon substrate, an III-V compound semiconductor substrate, or the like), the semiconductor substrate comprising a functional region (device area 518, Figure 14) and a seal ring region (inactive area 551, Figure 14); manufacturing a first metallization layer (interconnect structure 526, Figure 14), the first metallization layer comprising a first portion within the functional region and a second portion within the seal ring region, the first portion being separated from the second portion (Figure 14); forming a first bond layer (bond dielectric layer 540, Figure 14), the forming the first bond layer comprising: forming first bond pads (bond pads 542, Figure 14) within the functional region; and forming a first bond metal (ring-like bond pads 552 + bond pad vias 554, Figure 14) within the seal ring region, the first bond metal and the second portion of the first metallization layer forming a first seal ring (ring-like bond pads 552 + pond pad vias 654 + seal ring unit 536, Figure 14); and bonding the first bond metal to a second bond metal within a semiconductor wafer (ring-like bond pads 652 + bond pad vias 654, Figure 14), as claimed.
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Regarding claim 9, Hu (US Patent No 10,312,201) teaches the method of claim 8, as claimed. Hu (US Patent No 10,312,201) further teaches wherein the forming the first bond layer further comprises forming first bond vias (bond pad vias 554 + bond pad vias 544, Figure 14), as claimed.
Regarding claim 10, Hu (US Patent No 10,312,201) teaches the method of claim 8, as claimed. Hu (US Patent No 10,312,201) further teaches wherein the first bond metal has a first configuration and the second bond metal has the first configuration (col 20 lines 65-66 + col 19 lines 46-55, Figure 14, teaches Die has similar features as die...Wafer and dies are substantially similar to the wafer and dies, except as described below. Accordingly, the details for dies are omitted for the sake of brevity. Referring to FIG. 13a, die contains similar features and structures as dies including a seal ring unit, device area, and bond pads. In addition, die includes additional ring-like bond pads. Ring-like bond pads include a ring-like structure disposed over and coupled to each of the seal ring unit), as claimed.
Regarding claim 11, Hu (US Patent No 10,312,201) teaches the method of claim 8, as claimed. Hu (US Patent No 10,312,201) further teaches further comprising encapsulating the semiconductor substrate with an encapsulant (Figure 14, col4, lines 8-13, teaches A device area is formed at the surface or inside substrate...device area may comprise an encapsulated die), as claimed.
Regarding claim 21, Hu (US Patent No 10,312,201) teaches a method of manufacturing a semiconductor device (die package 613, Figure 14), the method comprising: forming a first semiconductor device (die 512, Figure 14), the first semiconductor device comprising a functional region (device area 518, Figure 14) and a seal ring region (inactive area 551, Figure 14) surrounding the functional region, the functional region comprising active devices (col 4, lines 10-11, teaches Device area may comprise active or passive devices, such as transistors, resistors, capacitors, diodes, and the like), forming the first semiconductor device comprising: forming a first interconnect structure (interconnect structure 526, Figure 14) over a first substrate (substrate 522, Figure 14), the first interconnect structure comprising first electrical wirings electrically connected to the active devices and a first part of a seal ring surrounding the functional region (Figure 14); and forming a first bond layer (bond dielectric layer 540, Figure 14), the first bond layer comprising first bond pads (bond pad 542 + bond pad vias 544, Figure 14) electrically connected to the first electrical wirings of the first interconnect structure and a first seal ring bond pad (ring-like bond pads 552 + bond pad vias 554, Figure 14) forming a second part of the seal ring surrounding the functional region; forming a second semiconductor device (die 612, Figure 14), the second semiconductor device comprising a second substrate (substrate 622, Figure 14), a second bond layer (bond dielectric layer 640, Figure 14) over the second substrate, second bond pads (bond pads 642 + bond pad vias 644, Figure 14) in the second bond layer, and a second seal ring bond pad (ring-like bond pad 652 + bond pad vias 654, Figure 14) in the second bond layer; bonding the first bond pads of the first semiconductor device to the second bond pads of the second semiconductor device (Figure 14, col 19, lines 64-65, teaches die is bonded to a similarly formed die); and bonding the first seal ring bond pad of the first semiconductor device to the second seal ring bond pad of the second semiconductor device (Figure 14, col 19, lines 64-65, teaches die is bonded to a similarly formed die), as claimed.
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Regarding claim 24, Hu (US Patent No 10,312,201) teaches the method of claim 21, as claimed. Hu (US Patent No 10,312,201) further teaches wherein the first bond layer comprises an outer ring surrounding the seal ring (Figure 13c), as claimed.
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Regarding claim 25, Hu (US Patent No 10,312,201) teaches the method of claim 24, as claimed. Hu (US Patent No 10,312,201) further teaches wherein the outer ring is not connected to the seal ring in the first interconnect structure, as claimed.
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Regarding claim 26, Hu (US Patent No 10,312,201) teaches the method of claim 21, as claimed. Hu (US Patent No 10,312,201) further teaches further comprising: encapsulating the first semiconductor device (Figure 14, col4, lines 8-13, teaches A device area is formed at the surface or inside substrate...device area may comprise an encapsulated die), as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-6, 14, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US Patent No 10,312,201) in view of Wang (US Patent No 7,607,586).
Regarding claim 3, Hu (US Patent No 10,312,201) teaches the method of claim 1, as claimed.
Hu (US Patent No 10,312,201) is silent to teach wherein the first seal ring has an octagonal shape.
In an analogous art, Wang (US Patent No 7,607,586) teaches wherein the first seal ring has an octagonal shape (seal ring area 85, Figure 2), as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Hu (US Patent No 10,312,201) with the teachings of Wang (US Patent No 7,607,586) thereby having a first seal ring with an octagonal shape.
Regarding claim 4, Hu (US Patent No 10,312,201) and Wang (US Patent No 7,607,586) teach the method of claim 3, as claimed. Wang (US Patent No 7,607,586) further teaches wherein the octagonal shape comprises a first tilted side located along a corner of the functional region (Figure 2), as claimed.
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Regarding claim 5, Hu (US Patent No 10,312,201) and Wang (US Patent No 7,607,586) teach the method of claim 4, as claimed. Wang (US Patent No 7,607,586) further teaches wherein the octagonal shape comprises a second tilted side located along the corner of the functional region (Figure 2), as claimed.
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Regarding claim 6, Hu (US Patent No 10,312,201) and Wang (US Patent No 7,607,586) teach the method of claim 3, as claimed. Wang (US Patent No 7,607,586) further teaches wherein the first seal ring has a second octagonal shape surrounding the octagonal shape (Figure 2), as claimed.
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Regarding claim 14, Hu (US Patent No 10,312,201) teaches the method of claim 8, as claimed.
Hu (US Patent No 10,312,201) is silent to teach wherein the forming the first bond metal forms the first bond metal in an octagonal shape.
In an analogous art, Wang (US Patent No 7,607,586) teaches wherein the forming the first bond metal (antenna 41, Figure 2, col 4 lines 52-54 + col 20 lines 25-28, teaches The antenna is formed of wire, printed conductors, seal rings or other structures on, below or above the top plane of the semiconductor chip...The rectangular loop shape of the antenna is shown by way of example. Any other shape such as circular, square, hexagonal and octagonal may be employed that can effectively receive and transmit electromagnetic signals) forms the first bond metal in an octagonal shape, as claimed.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Hu (US Patent No 10,312,201) with the teachings of Wang (US Patent No 7,607,586) thereby forming the bond metal into an octagonal shape.
Regarding claim 22, Hu (US Patent No 10,312,201) teaches the method of claim 21, as claimed.
Hu (US Patent No 10,312,201) is silent to teach wherein the seal ring has an octagonal shape, wherein the octagonal shape comprises extended sides extending parallel to sides of the functional region and first tilted sides connecting adjacent ones of the extended sides.
In an analogous art, Wang (US Patent No 7,607,586) teaches wherein the seal ring has an octagonal shape (seal ring area 85, Figure 2), wherein the octagonal shape comprises extended sides extending parallel to sides of the functional region and first tilted sides connecting adjacent ones of the extended sides (seal ring area 85, Figure 2), as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Hu (US Patent No 10,312,201) with the teachings of Wang (US Patent No 7,607,586) thereby having a seal ring with an octagonal shape.
Regarding claim 23, Hu (US Patent No 10,312,201) and Wang (US Patent No 7,607,586) teach the method of claim 22, as claimed. Wang (US Patent No 7,607,586) further teaches wherein the octagonal shape further comprises second tilted sides spaced apart from and parallel to the first tilted sides (Figure 2), as claimed.
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Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US Patent No 10,312,201) in view of Chen (US Patent No 11, 862,590).
Regarding claim 12, Hu (US Patent No 10,312,201) teaches the method of claim 11, as claimed.
Hu (US Patent No 10,312,201) is silent to teach further comprising thinning the semiconductor wafer to expose through vias after the bonding.
In an analogous art, Chen (US Patent No 11,862,590) teaches further comprising thinning the semiconductor wafer to expose through vias after the bonding (Figure 6F, col 26, lines 16-18, teaches a planarization step such as CMP, or the like, may then be performed to expose the conductive vias of the bottom wafer), as claimed.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Hu (US Patent No 10,312,201) by using the wafer thinning process of Chen (US Patent No 11,862,590) thereby exposing the substrate vias for device connection with external communication or redistribution layers.
Regarding claim 13, Hu (US Patent No 10,312,201) teaches the method of claim 12, as claimed. Chen (US Patent No 11,862,590) further teaches further comprising forming a first redistribution structure in electrical connection with the through vias (structure 310, Figure 7A, col 27, lines 29-33, teaches an integrated circuit package, in which a stack and a HBM device are shown bonded and electrically connected to a structure using conductive connectors and conductive connectors, respectively), as claimed.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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