DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 3 is objected to because of the following informalities: “..vertical plane that contains a respective sidewall of the top electrode”. Perhaps, “top electrode” should be replaced with “first electrode”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over INO et al. (US PGpub: 2020/0091160 A1), herein after INO, in view of INO.
Regarding claim 1, INO teaches a device structure comprising, from bottom to top:
a first electrode (54,FIG. 6);
a ferroelectric layer (18); and
a second electrode (52, FIG. 6).
INO does not explicitly teach an interface metal layer configured induce formation of an orthorhombic crystal phase in the ferroelectric layer.
However, INO teaches interface metal layer configured induce formation of an orthorhombic crystal phase in the ferroelectric layer. (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure..);
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use INO’s device structure with other teaching from INO in order to memory cell capacity is improved.
Regarding claim 2, INO teaches the device structure of Claim 1, wherein the interface metal layer comprises tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum nitride (TaN), or a combination thereof ((The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure.).
Regarding claim 3, INO teaches the device structure of Claim 1, wherein all sidewalls of the interface metal layer are located within a respective vertical plane that contains a respective sidewall of the first electrode (since interface metal material layer is within ferroelectric layer as described in Paragraph [0029], all sidewalls of the interface metal layer will definitely be located within a respective vertical plane that contains a respective sidewall of the top electrode as in FIG. 6) .
Regarding claim 4, INO teaches the device structure of Claim 1, further comprising a high-k dielectric layer (19, the paraelectric layer 19 includes a paraelectric. The paraelectric is, for example, oxide or oxynitride. The paraelectric is, for example, silicon oxide. Oxynitride can be a high-k dielectric) interposed between the ferroelectric layer (18 and the first electrode (52).
Regarding claim 5, INO teaches the device structure of Claim 4, wherein the high-k dielectric layer (19, the paraelectric layer 19 includes a paraelectric. The paraelectric is, for example, oxide or oxynitride. The paraelectric is, for example, silicon oxide. Oxynitride can be a high-k dielectric) is in contact with the ferroelectric layer (18) and the first electrode (54).
Regarding claim 6, INO teaches the device structure of Claim 4, wherein the stack comprises a ferroelectric tunnel junction (Paragraphs [0142]-[0148], [0130]).
Regarding claim 7, INO teaches the device structure of Claim 6, further comprising a field effect transistor, wherein the first electrode is electrically connected to a drain region of the field effect transistor (lower capacitor electrode 40 is provided on the drain region 14 in FIG. 5).
Regarding claim 8, INO teaches the device structure of Claim 1, wherein the ferroelectric layer comprises HfO, HfO2, HfZrO, Pb[ZrxTi1-x]O3, (0 ≤ x ≤ 1), PbTiO3, HfLaO, or a combination thereof (. By the examination using the first principle calculation of the inventor, it has been found that the κ-aluminum oxide contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), so that heat resistance of the κ-aluminum oxide is improved. Paragraph [0067]. … The aluminum oxide has a wider band gap than hafnium oxide applied as the ferroelectric in the past. The band cap of ferroelectric the third orthorhombic hafnium oxide is calculated as only the degree of about 6 eV, the band gap of ferroelectric κ-aluminum oxide is calculated more than 8 eV depending on the inventors first principle calculation. The wider band gap gives the higher breakdown voltage. Therefore, the aluminum oxide has a higher dielectric breakdown voltage than the hafnium oxide. Therefore, the aluminum oxide is applied to the ferroelectric layer 18, so that a memory device with high reliability is realized. paragraph [0080]).
Regarding claim 9, INO teaches the device structure of Claim 1, further comprising a field effect transistor located on a semiconductor layer (10) and including a portion of the semiconductor layer as a channel region in contact with the ferroelectric layer (10 is electrically in contact with 19, FIG. 3-, 5-6), wherein the first electrode (52) comprises a drain region (14, FIG. 5) of the field effect transistor.
Regarding claim 10, INO teaches the device structure of Claim 1, wherein: the ferroelectric layer comprises vertically-extending portions that laterally surround the interface metal layer; the interface metal layer comprises vertically-extending portions that laterally surround the second electrode ((The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The W or Ru layer is the interface layer. The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure…. The interface layer is within the ferroelectric layer 18, so it will have horizontal or all portion will overlie channel layer obviously. And vertically-extending portions that laterally surround the second electrode 54); and topmost surfaces of the second electrode (54) , the interface metal layer, and the ferroelectric layer are located within a same horizontal plane. (54, interface metal layer within 18 and 18 all situated in same plane)
Regarding claim 11, INO teaches a device structure comprising a ferroelectric tunnel junction which comprises;
a first electrode (54,FIG. 6);
a ferroelectric layer (18) overlying the first electrode (54); and
a second electrode (52) overlying the interface metal layer.
INO does not explicitly teach an interface metal layer overlying the ferroelectric layer and configured induce formation of an orthorhombic crystal phase in the ferroelectric layer;.
However, INO teaches an interface metal layer overlying the ferroelectric layer and configured induce formation of an orthorhombic crystal phase in the ferroelectric layer; (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure..);
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use INO’s device structure with other teaching from INO in order to memory cell capacity is improved.
Regarding claim 12, INO teaches the device structure of Claim 11, wherein the interface metal layer comprises tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum nitride (TaN), or a combination thereof (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure..).
Regarding claim 13, INO teaches the device structure of Claim 11, further comprising a first dielectric layer (19) interposed between the ferroelectric layer and the first electrode.
Regarding claim 14, INO teaches the device structure of Claim 11, further comprising a field effect transistor (FET memory stack ) located on a semiconductor layer (10) and including a portion of the semiconductor layer as a channel region (top portion of 10 is channel layer as well) in contact with the ferroelectric layer (10 is electrically connected to 18), wherein the first electrode (52) comprises a drain region (14) of the field effect transistor (as in FIG. 5).
Regarding claim 15, INO teaches the device structure of Claim 11, further comprising: a first dielectric layer (13) underlying the first electrode and having a greater lateral extent than the first electrode(FIG. 6); and an encapsulation layer (30, FIG. 5) comprising a dielectric material and laterally surrounding and covering each of the first electrode, the ferroelectric layer, the interface metal layer, and the second electrode (See FIG. 5 where 30 is covering all of the layers)..
Regarding claim 16, INO teaches a device structure comprising:
a source region (12, FIG. 5) and a drain region (14) that are spaced apart from each other by a channel region (10, The semiconductor layer 10 functions as a channel of the memory cell transistor MT in Paragraph [0098]);
a ferroelectric layer (18, FIG. 5 and 6) overlying the channel region; and
an interface metal layer located on the ferroelectric layer and configured induce formation of an orthorhombic crystal phase in the ferroelectric layer (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure..); and
a gate electrode (54, FIG. 6) located on the interface metal layer.
Since FIG. 5 and FIG 6 are different embodiments and source/drain now shown in FIG. 5, INO’s device structure can be modified with other teaching from INO in order to memory cell capacity is improved.
Regarding claim 17, INO teaches the device structure of Claim 16, wherein the interface metal layer comprises tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum nitride (TaN), or a combination thereof (Paragraph [0029] The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029].).
Regarding claim 18, INO teaches the device structure of Claim 16, wherein the ferroelectric layer comprises a horizontally-extending portion that overlies a top surface of the channel region, and vertically-extending portions contacting sidewalls of the channel region (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The W or Ru layer is the interface layer. The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure…. The interface layer is within the ferroelectric layer 18, so it will have horizontal or all portion will overlie channel layer obviously. And vertical portion will contact sidewall of the channel layer).
Regarding claim 19, INO teaches the device structure of Claim 18, wherein the interface metal layer comprises a horizontally-extending portion that overlies the horizontally-extending portion of the ferroelectric layer, and vertically-extending portions contacting outer sidewalls of the vertically-extending portions of the ferroelectric layer (The aluminum oxide of the ferroelectric layer 18 contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru). The W or Ru layer is the interface layer. The content of the first element in the aluminum oxide is, for example, 1 atomic percent to 9 atomic percent in Paragraph [0029]. Ferroelectric layer 18 contains ferroelectric aluminum oxide. The ferroelectric layer 18 contains ferroelectric aluminum oxide as a main component. The κ-aluminum oxide has an orthorhombic crystal structure…. The interface layer is within the ferroelectric layer 18, so it will have horizontal or all portion will overlie channel layer obviously. And vertically-extending portions contacting outer sidewalls of the vertically-extending portions of the ferroelectric layer).
Regarding claim 20, INO teaches the device structure of Claim 16, wherein the channel region, the ferroelectric layer, the interface metal layer, and the gate electrode comprises a ferroelectric tunnel junction (Paragraphs [0142]-[0148], [0130]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHEIKH MARUF/Primary Examiner, Art Unit 2897
Prosecution Insights