Prosecution Insights
Last updated: July 17, 2026
Application No. 18/417,120

ARRANGEMENTS OF MULTIPLE-JUNCTION LIGHT-EMITTING DIODE CHIPS IN LIGHT-EMITTING DIODE PACKAGES AND RELATED DISPLAYS

Non-Final OA §102§103
Filed
Jan 19, 2024
Examiner
SALERNO, SARAH KATE
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
644 granted / 878 resolved
+5.3% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
28 currently pending
Career history
910
Total Applications
across all art units

Statute-Specific Performance

§103
84.6%
+44.6% vs TC avg
§102
13.7%
-26.3% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 878 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim et al. (US PGPub 2020/0350477). Claim 11: Shim teaches (Fig. 7-9A) a light-emitting diode (LED) package comprising: a support element (110); at least one single-junction LED chip (710)on the support element; at least one multiple-junction LED chip (111) on the support element; and an electrically conductive element on the support element, the electrically conductive element forming a common anode connection or a common cathode connection for the at least one single-junction LED chip and the at least one multiple-junction LED chip [0109, 0127]. Claim 20: Shim teaches (Fig. 7-9A) A light-emitting diode (LED) display comprising: a display panel; and at least one LED package comprising: at least one single-junction LED chip; and at least one multiple-junction LED chip, the at least one single-junction LED chip and the at least one multiple-junction LED chip forming a pixel of the display panel. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Grave et al. (US PGPub 2021/0153322). Claim 1: Grave teaches (Fig. 3-6) (Claims 16-27) a light-emitting diode (LED) package comprising: a support element [0026]; at least one single-junction LED chip on the support element, the at least one single- junction LED chip comprising a first forward voltage; and at least one multiple-junction LED chip on the support element, the at least one multiple- junction LED chip comprising at least two light-emitting junctions, the at least two light-emitting junctions being electrically coupled in series (Claim 27) [0027], and the at least one multiple-junction LED chip comprising a second forward voltage that is within twenty five percent of the first forward voltage (Claim 22). Since it has been held when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on ranges by showing unexpected results or the criticality of the claimed range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claim. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F. 2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 716.02-716.02(g) for a discussion of criticality and unexpected results. The forward voltage requirements could be discovered through routine experimentation. Claim 2: Grave teaches (Fig. 3-6) (Claims 16-27) the second forward voltage is within fifteen percent of the first forward voltage. Since it has been held when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on ranges by showing unexpected results or the criticality of the claimed range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claim. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F. 2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 716.02-716.02(g) for a discussion of criticality and unexpected results. The forward voltage requirements could be discovered through routine experimentation. Claim 3: Grave teaches (Fig. 3) (Claims 16-27) [0026] an electrically conductive element on the support element, the electrically conductive element forming a common anode connection or a common cathode connection for the at least one single-junction LED chip and the at least one multiple-junction LED chip. Claim 4: Grave teaches (Fig. 3) (Claims 16-27) [0026] the support element is a submount with a plurality of patterned traces on a surface of the submount. Claim 5: Grave teaches (Fig. 3) (Claims 16-27) [0026] the support element is a lead frame structure comprising a lead frame and housing, and the electrically conductive element is a single lead of the lead frame. Claim 6: Grave teaches (Fig. 3) (Claims 16-27) [0026] at least one single-junction LED chip and the at least one multiple-junction LED chip are electrically coupled with the electrically conductive element by way of a wire bond. Claim 7: Grave teaches (Fig. 3) (Claims 16-27) [0026] at least one of the at least one single- junction LED chip and the at least one multiple-junction LED chip is flip-chip mounted and electrically coupled with the electrically conductive element. Claim 8: Grave teaches (Fig. 3) the support element comprises a lead frame structure, and the at least one single-junction LED chip is electrically coupled to a different pair of leads of the lead frame structure than the at least one multiple-junction LED chip. Claim 9: Grave teaches (Fig. 3) [0003, 0020, 0030] the at least one single-junction LED chip is configured to emit light of a first peak wavelength; and the at least one multiple-junction LED chip is configured to emit light of a second peak wavelength, and the second peak wavelength differs from the first peak wavelength by at least 20 nanometers (nm). Claim 10: Grave teaches (Fig. 3) [0003, 0020, 0030] an additional multiple-junction LED chip configured to emit light of a third peak wavelength that differs from the first peak wavelength and the second peak wavelength by at least 20 nm; and an additional single-junction LED chip configured to emit light of a fourth peak wavelength that differs from the first peak wavelength, the second peak wavelength, and the third peak wavelength by at least 20 nm; wherein the additional multiple-junction LED chip comprises a third forward voltage that is within twenty five percent of the first forward voltage and the second forward voltage. Claim(s) 12-19 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over, as applied to claim Shim et al. (US PGPub 2020/0350477) above, and further in view of Grave et al. (US PGPub 2021/0153322). Regarding claim 12, as described above, Shim substantially reads on the invention as claimed, except Shim does not teach the support element is a submount and the electrically conductive element is a patterned trace on a surface of the submount. Grave teaches the support element is a submount and the electrically conductive element is a patterned trace on a surface of the submount as a common support for an LED. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Shim to have used a submout as claimed because it is commonly used in the art. Claim 13: Grave teaches (Fig. 3) (Claims 16-27) [0026] the support element is a lead frame structure comprising a lead frame and housing, and the electrically conductive element is a single lead of the lead frame. Claim 14: Grave teaches (Fig. 3) (Claims 16-27) [0026] the support element comprises a lead frame structure, and the at least one single-junction LED chip is electrically coupled to a different pair of leads of the lead frame structure than the at least one multiple-junction LED chip. Claim 15: Grave teaches (Fig. 3) (Claims 16-27) [0026] at least one of the at least one single- junction LED chip and the at least one multiple-junction LED chip is electrically coupled with the electrically conductive element by way of a wire bond. Claim 16: Grave teaches (Fig. 3) (Claims 16-27) [0026] at least one of the at least one single- junction LED chip and the at least one multiple-junction LED chip is flip-chip mounted and electrically coupled with the electrically conductive element. Claim 17: Grave teaches (Fig. 3) [0003, 0020, 0030] the at least one single-junction LED chip is configured to emit light of a first peak wavelength; and the at least one multiple-junction LED chip is configured to emit light of a second peak wavelength, and the second peak wavelength differs from the first peak wavelength by at least 20 nanometers (nm). Claim 18: Grave teaches (Fig. 3) [0003, 0020, 0030] an additional multiple-junction LED chip configured to emit light of a third peak wavelength that differs from the first peak wavelength and the second peak wavelength by at least 20 nm; wherein the electrically conductive element forms the common anode connection or the common cathode connection for the single-junction LED chip, the multiple-junction LED chip, and the additional multiple-junction LED chip. Claim 19: Grave teaches (Fig. 3) [0003, 0020, 0030] an additional single-junction LED chip configured to emit light of a fourth peak wavelength that differs from the first peak wavelength, the second peak wavelength, and the third peak wavelength by at least 20 nm; wherein the electrically conductive element forms the common anode connection or the common cathode connection for the single-junction LED chip, the additional single-junction LED chip, the multiple-junction LED chip, and the additional multiple-junction LED chip. Claim 21: Grave teaches (Fig. 3) [0003, 0020, 0030] at least one of the at least one single- junction LED chip and the at least one multiple-junction LED chip is electrically coupled to a common anode connection or a common cathode connection. Claim 22: Grave teaches (Fig. 3) [0003, 0020, 0030] the at least one single-junction LED chip comprises a first forward voltage; and the at least one multiple-junction LED chip comprises a second forward voltage that is within twenty five percent of the first forward voltage. Since it has been held when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on ranges by showing unexpected results or the criticality of the claimed range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claim. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F. 2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 716.02-716.02(g) for a discussion of criticality and unexpected results. The forward voltage requirements could be discovered through routine experimentation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARAH K SALERNO/Primary Examiner, Art Unit 2814
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Prosecution Timeline

Jan 19, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
88%
With Interview (+14.8%)
2y 11m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 878 resolved cases by this examiner. Grant probability derived from career allowance rate.

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