DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-15 in the reply filed on 6/12/2026 is acknowledged. The traversal is on the ground(s) that the amendment to claim 13 joins Group II with Group I. This is found persuasive and the group of claims 1-15 have been examined herein. Applicant does not provide any arguments with respect to non-elected Group III (claims 16-20) and claims 16-20 have been withdrawn, accordingly.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vasquez et al. U.S. PGPUB No. 2019/0280193 in view of Krishnan et al. U.S. PGPUB No. 2018/0142356.
Regarding claim 1, Vasquez discloses a measurement system for measuring temperatures applicable for semiconductor manufacturing, comprising: a substrate support assembly comprising: an inner section 505 comprising: a first face (the face that is visible in figure 5), a second face opposing the first face (the face on the opposite side, that is not pictured in figure 5), one or more first support recesses 521 and 522 formed in the first face (“A step 521 or 522 is formed around the perimeter of each cutout 511 or 512 so that a wafer can sit and be supported thereon” [0040]) , and one or more openings 511 and 512 extending between the one or more first support recesses 521 and 522 and the second face (as illustrated in figure 5), and an outer section 503 configured to support an outer region of the inner section 505 (as illustrated in figure 5); one or more calibration substrates sized and shaped for positioning at least partially in the one or more first support recesses 511 and 512 (“an entire 100 mm wafer can sits on the step and entirely fits in the cutout (e.g., see the wafers fitting in the horizontal substrate adaptors in FIG. 2)” [0040]). However, there is no explicit disclosure of a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy.
Krishnan discloses a “Susceptor 110 [that] has a generally circular cross-section” [0045], wherein “Susceptor 110 can be a single wafer carrier retention system holding a single wafer 106 or can support multiple wafers” [0044] (as illustrated in figure 1A with respect to susceptor 24). Krishnan includes a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy (“Light source 401 directs while light through viewport 403 into reactor chamber 404. Light directed in this way illuminates epitaxial layer 405 being grown on wafer 406. The illuminated wafer reflects light back through viewport 403 into detector 402. Based on the measurement of the reflected light, controller 407 adjusts one or more flows to the reactor chamber 404” [0063]).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate support assembly of Vasquez (which relates generally to “semiconductor processing and equipment, and more particularly, to devices for holding semiconductor substrates for processing” [Vasquez: 0001]) with the substrate support assembly of Krishnan (“A number of process parameters are controlled, such as temperature, pressure and gas flow rate, to achieve a desired crystal growth. Different layers are grown using varying materials and process parameters. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition (MOCVD)” [Krishnan: 0004]), including an energy source and a band edge detector, in order to provide feedback relating to a processing of a semiconductor substrate during a method of processing a semiconductor substrate.
Regarding claim 2, Vasquez discloses the claimed invention except that while Vasquez discloses that the one or more calibration substrates comprise a plurality of calibration substrates (“A step 521 or 522 is formed around the perimeter of each cutout 511 or 512 so that a wafer can sit and be supported thereon. In this configuration, as the horizontal substrate adaptor 500 is placed horizontally (e.g., as sitting in a slot of a 300 mm wafer cassette), an entire 100 mm wafer can sits on the step and entirely fits in the cutout (e.g., see the wafers fitting in the horizontal substrate adaptors in FIG. 2)” [0040]), there is no explicit disclosure that at least two of the calibration substrates have different band gap materials.
Krishnan discloses “Other semiconductor layers, such as SiN, TiN, InGaN, GaAs and the like, which are formed from Group II, Group IV, Group V, and Group VI elements, can be formed and analyzed within the current system and method. Semiconductor layers formed from of the foregoing can be undoped, p-doped (with, for example, boron, aluminum, nitrogen, gallium, magnesium, and indium), or n-doped (with, for example, phosphorus, arsenic, and carbon)” [0004].
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate support assembly of Vasquez with the substrate support assembly of Krishnan for processing different compositions of substrates in order to provide analyses of various types of substrates instead of a single type of substrate.
Regarding claim 8, Vasquez discloses the claimed invention except that there is no explicit disclosure of a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy.
Krishnan discloses a “Susceptor 110 [that] has a generally circular cross-section” [0045], wherein “Susceptor 110 can be a single wafer carrier retention system holding a single wafer 106 or can support multiple wafers” [0044] (as illustrated in figure 1A with respect to susceptor 24). Krishnan includes a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy wherein the first energy is light, and the light is reflected off of at least one of the one or more calibration substrates before being received by the band edge detector (“Light source 401 directs while light through viewport 403 into reactor chamber 404. Light directed in this way illuminates epitaxial layer 405 being grown on wafer 406. The illuminated wafer reflects light back through viewport 403 into detector 402. Based on the measurement of the reflected light, controller 407 adjusts one or more flows to the reactor chamber 404” [0063]).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate support assembly of Vasquez (which relates generally to “semiconductor processing and equipment, and more particularly, to devices for holding semiconductor substrates for processing” [Vasquez: 0001]) with the substrate support assembly of Krishnan (“A number of process parameters are controlled, such as temperature, pressure and gas flow rate, to achieve a desired crystal growth. Different layers are grown using varying materials and process parameters. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition (MOCVD)” [Krishnan: 0004]), including an energy source and a band edge detector, in order to provide feedback relating to a processing of a semiconductor substrate during a method of processing a semiconductor substrate.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vasquez et al. U.S. PGPUB No. 2019/0280193 in view of Krishnan et al. U.S. PGPUB No. 2018/0142356 in further view of Ma et al. U.S. PGPUB No. 2020/0013586.
Regarding claim 13, Vasquez discloses a system for processing substrates applicable for semiconductor manufacturing (“Embodiments of the present application relate to semiconductor processing and equipment, and more particularly, to devices for holding semiconductor substrates for processing” [0001]), the system comprising: a chamber body 101 comprising one or more sidewalls (as illustrated in figure 1), the one or more sidewalls at least partially defining an internal volume (as illustrated in figure 1); one or more heat sources configured to heat the internal volume (“the annealing chamber 101 is maintained under vacuum and heated to a preset temperature” [0027]); the substrate support assembly of claim 1 disposed in the internal volume (as illustrated in figure 1, and discussed with respect to the rejection of claim 1, above), wherein: the one or more first support recesses 521 and 522 comprise a plurality of first support recesses formed in the first face (as illustrated in figure 5), and the one or more openings 511 and 512 comprise a plurality of openings extending between the plurality of first support recesses and the second face (as illustrated in figure 5). Vasquez discloses the claimed invention except that there is no explicit disclosure that the chamber comprises a lid and a window.
Krishnan discloses that “A window or viewport (item 30 in FIG. 1A; item 300 in FIG. 1B) is arranged in the top surface of reactor housing 10 or reactor 140” [0048]. It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Vasquez with the window of Krishnan in order to view the results of semiconductor processing so as to inform a user about the status of the processing. Vasquez and Krishnan disclose the claimed invention except that there is no explicit disclosure of a lid.
Ma discloses a “semiconductor processing apparatus 108” [0025] including a “chamber lid 106” [0025]. It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Vasquez and Krishnan with the lid of Ma in order to provide an access port to a chamber so as to selectively insert and/or remove substrates and/or other components.
Regarding claim 14, Vasquez discloses the claimed invention except that while Vasquez discloses that the one or more calibration substrates comprise a plurality of calibration substrates (“A step 521 or 522 is formed around the perimeter of each cutout 511 or 512 so that a wafer can sit and be supported thereon. In this configuration, as the horizontal substrate adaptor 500 is placed horizontally (e.g., as sitting in a slot of a 300 mm wafer cassette), an entire 100 mm wafer can sits on the step and entirely fits in the cutout (e.g., see the wafers fitting in the horizontal substrate adaptors in FIG. 2)” [0040]), there is no explicit disclosure that at least two of the calibration substrates have different band gap materials.
Krishnan discloses “Other semiconductor layers, such as SiN, TiN, InGaN, GaAs and the like, which are formed from Group II, Group IV, Group V, and Group VI elements, can be formed and analyzed within the current system and method. Semiconductor layers formed from of the foregoing can be undoped, p-doped (with, for example, boron, aluminum, nitrogen, gallium, magnesium, and indium), or n-doped (with, for example, phosphorus, arsenic, and carbon)” [0004].
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate support assembly of Vasquez with the substrate support assembly of Krishnan for processing different compositions of substrates in order to provide analyses of various types of substrates instead of a single type of substrate.
Allowable Subject Matter
Claims 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3; Vasquez et al. U.S. PGPUB No. 2019/0280193 discloses a measurement system for measuring temperatures applicable for semiconductor manufacturing, comprising: a substrate support assembly comprising: an inner section 505 comprising: a first face (the face that is visible in figure 5), a second face opposing the first face (the face on the opposite side, that is not pictured in figure 5), one or more first support recesses 521 and 522 formed in the first face (“A step 521 or 522 is formed around the perimeter of each cutout 511 or 512 so that a wafer can sit and be supported thereon” [0040]) , and one or more openings 511 and 512 extending between the one or more first support recesses 521 and 522 and the second face (as illustrated in figure 5), and an outer section 503 configured to support an outer region of the inner section 505 (as illustrated in figure 5); one or more calibration substrates sized and shaped for positioning at least partially in the one or more first support recesses 511 and 512 (“an entire 100 mm wafer can sits on the step and entirely fits in the cutout (e.g., see the wafers fitting in the horizontal substrate adaptors in FIG. 2)” [0040]). However, there is no explicit disclosure of a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy.
Krishnan et al. U.S. PGPUB No. 2018/0142356 discloses a “Susceptor 110 [that] has a generally circular cross-section” [0045], wherein “Susceptor 110 can be a single wafer carrier retention system holding a single wafer 106 or can support multiple wafers” [0044] (as illustrated in figure 1A with respect to susceptor 24). Krishnan includes a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy (“Light source 401 directs while light through viewport 403 into reactor chamber 404. Light directed in this way illuminates epitaxial layer 405 being grown on wafer 406. The illuminated wafer reflects light back through viewport 403 into detector 402. Based on the measurement of the reflected light, controller 407 adjusts one or more flows to the reactor chamber 404” [0063]). However, Krishnan does not disclose an inner calibration substrate having a first band gap material, anda plurality of outer calibration substrates positioned outwardly of the inner calibration substrate and along a circumferential pattern, the plurality of outer calibration substrates comprising: a second calibration substrate having a second band gap material, a third calibration substrate having a third band gap material, a fourth calibration substrate having a fourth band gap material, and a fifth calibration substrate having a fifth band gap material.
The prior art fails to teach or reasonably suggest, in combination with the other claim limitations, a measurement system for measuring temperatures applicable for semiconductor manufacturing, comprising: a substrate support assembly comprising: an inner section comprising: a first face, a second face opposing the first face, one or more first support recesses formed in the first face, and one or more openings extending between the one or more first support recesses and the second face; one or more calibration substrates sized and shaped for positioning at least partially in the one or more first support recesses; wherein: the one or more calibration substrates an inner calibration substrate having a first band gap material, and a plurality of outer calibration substrates positioned outwardly of the inner calibration substrate and along a circumferential pattern, the plurality of outer calibration substrates comprising: a second calibration substrate having a second band gap material, a third calibration substrate having a third band gap material, a fourth calibration substrate having a fourth band gap material, and a fifth calibration substrate having a fifth band gap material.
Regarding claims 4, 5, 6, and 7; these claims would be allowable at least for their dependence, either directly or indirectly, upon claim 3.
Regarding claim 9; Vasquez et al. U.S. PGPUB No. 2019/0280193 discloses a measurement system for measuring temperatures applicable for semiconductor manufacturing, comprising: a substrate support assembly comprising: an inner section 505 comprising: a first face (the face that is visible in figure 5), a second face opposing the first face (the face on the opposite side, that is not pictured in figure 5), one or more first support recesses 521 and 522 formed in the first face (“A step 521 or 522 is formed around the perimeter of each cutout 511 or 512 so that a wafer can sit and be supported thereon” [0040]) , and one or more openings 511 and 512 extending between the one or more first support recesses 521 and 522 and the second face (as illustrated in figure 5), and an outer section 503 configured to support an outer region of the inner section 505 (as illustrated in figure 5); one or more calibration substrates sized and shaped for positioning at least partially in the one or more first support recesses 511 and 512 (“an entire 100 mm wafer can sits on the step and entirely fits in the cutout (e.g., see the wafers fitting in the horizontal substrate adaptors in FIG. 2)” [0040]). However, there is no explicit disclosure of a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy.
Krishnan et al. U.S. PGPUB No. 2018/0142356 discloses a “Susceptor 110 [that] has a generally circular cross-section” [0045], wherein “Susceptor 110 can be a single wafer carrier retention system holding a single wafer 106 or can support multiple wafers” [0044] (as illustrated in figure 1A with respect to susceptor 24). Krishnan includes a band edge calibration assembly comprising: an energy source positioned to emit a first energy, and a band edge detector disposed adjacent to the energy source and positioned to receive the first energy (“Light source 401 directs while light through viewport 403 into reactor chamber 404. Light directed in this way illuminates epitaxial layer 405 being grown on wafer 406. The illuminated wafer reflects light back through viewport 403 into detector 402. Based on the measurement of the reflected light, controller 407 adjusts one or more flows to the reactor chamber 404” [0063]). However, Krishnan does not disclose a first temperature sensor disposed adjacent to the band edge calibration assembly and positioned to receive a second energy; and a controller configured to, for at least two of the plurality of calibration substrates: emit the light toward a respective calibration substrate, determine a band edge absorption wavelength from the light reflected off of the respective calibration substrate and received by the band edge detector, determine a calibration temperature using the determined band edge absorption wavelength, determine a first measured temperature based on the received second energy of the first temperature sensor, and calibrate the first temperature sensor by comparing the first measured temperature and the calibration temperature.
Ito U.S. PGPUB No. 2019/0141790 discloses a “heat treatment apparatus comprises: a chamber for receiving a substrate therein; a light irradiator for irradiating the substrate received in the chamber with light; a substrate temperature measuring part for measuring the temperature of the substrate by receiving infrared radiation emitted from the substrate” [0013]. However, Ito does not disclose determining a calibration temperature using a determined band edge absorption wavelength, determining a first measured temperature based on received second energy of the first temperature sensor, and calibrating the first temperature sensor by comparing the first measured temperature and the calibration temperature.
Jackson et al. U.S. PGPUB No. 6,679,946 discloses a substrate processing apparatus wherein “the band edge wavelength at which transmission begins is indicative of wafer temperature” [col. 6; lines 55-58]. However, Jackson does not disclose determining a calibration temperature using a determined band edge absorption wavelength, determining a first measured temperature based on received second energy of the first temperature sensor, and calibrating the first temperature sensor by comparing the first measured temperature and the calibration temperature.
The prior art fails to teach or reasonably suggest, in combination with the other claim limitations, a measurement system for measuring temperatures applicable for semiconductor manufacturing, comprising: a band edge calibration assembly comprising: an energy source positioned to emit light, and a band edge detector disposed adjacent to the energy source and positioned to receive light reflected off of at least one of the one or more calibration substrate; and a controller configured to, for at least two of the plurality of calibration substrates: emit the light toward a respective calibration substrate, determine a band edge absorption wavelength from the light reflected off of the respective calibration substrate and received by the band edge detector, determine a calibration temperature using the determined band edge absorption wavelength, determine a first measured temperature based on the received second energy of the first temperature sensor, and calibrate the first temperature sensor by comparing the first measured temperature and the calibration temperature.
Regarding claims 10, 11, and 12; these claims would be allowable at least for their dependence, either directly or indirectly, upon claim 9.
Regarding claim 15; claim 15 includes substantially similar limitations to those of claim 9 and would be allowable for the reasons indicated with respect to claim 9.
Conclusion
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/JASON L MCCORMACK/Examiner, Art Unit 2881
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