DETAILED ACTION
This Office action is in response to the election filed 20 March 2026. Claims 21-40 are currently pending; claim 41 was cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 21-40, in the reply filed on 20 March 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “at least some of the one or more routing layers communicatively couple a circuit element of one die of the plurality of dies to another circuit element of another die of the plurality of dies through interconnections formed by direct hybrid bonds between the substrate and the plurality of dies” as in claim 21, and similar limitations of claim 31; “the wafer substrate comprises one or more input/output (I/O) connectors that communicatively couple at least one circuit element of the plurality of dies to an external device” as in claim 24 and similar limitations of claim 35; “wherein the one or more I/O connectors comprises a plurality of interconnects disposed at a second side of the substrate opposite the first side, and wherein the microelectronic device further comprises an interposer connected to the plurality of interconnects” as in claim 25 and similar limitations of claim 36; “an additional semiconductor layer bonded over the plurality of dies” as in claim 27 and similar limitations of 37 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites “the first process node being a more advanced node than the second process node” in lines 7-8; it is unclear what constitutes a more “advanced” node. For the purposes of examination, it is assumed that the first process node is different from the second process node. Claims 22-30 depend directly or indirectly from claim 21 and thus also contain the above indefinite language.
Claim 31 recites “the first process node being a more advanced node than the second process node” in lines 7-8; it is unclear what constitutes a more “advanced” node. For the purposes of examination, it is assumed that the first process node is different from the second process node. Claims 32-40 depend directly or indirectly from claim 31 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 and 31-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0102251 A1 to DeLaCruz et al. (hereinafter “DeLaCruz”).
Regarding claim 21, as best understood, DeLaCruz (Fig. 5) discloses a microelectronic device comprising:
a plurality of dies 506/508/510/n (¶ 0095), each die of the plurality of dies comprising one or more circuit elements (¶ 0074); and a substrate 108 (¶ 0069) directly hybrid-bonded to the plurality of dies (¶ 0096), wherein:
the substrate 108 comprises one or more routing layers 512/514 (¶¶ 0074, 76);
each die of the plurality of dies is fabricated in a first process node (¶ 0087);
at least a portion of the substrate 108 is fabricated in a second process node (¶ 0072), the first process node being a more advanced node than the second process node (¶¶ 0072, 87); and
at least some of the one or more routing layers communicatively couple a circuit element of one die of the plurality of dies to another circuit element of another die of the plurality of dies (¶ 0079) through interconnections formed by direct hybrid bonds (¶ 0096) between the substrate and the plurality of dies (¶ 0079).
The limitations “fabricated in a first process node” and “fabricated in a second process node” are product-by-process limitations that do not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 22, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 21, wherein the circuit element of the die comprises a logic component (¶ 0090), and wherein the another circuit element of the another die comprises a memory component (¶ 0091 - “510 may be a memory device”) communicatively coupled to the logic component of the die (¶ 0091 - “510 has multiple independent functions and multiple ports that may communicate with a plurality of functional elements”) through the interconnections formed by the direct hybrid bonds between the substrate and the plurality of dies (¶ 0079 - “108 uses chiplets 506 & 508 & 510 . . . n and communicatively connects them together”).
Regarding claim 23, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 21, wherein the plurality of dies 506/508/510/n comprises two or more dies in a side-by-side arrangement (Fig. 5).
Regarding independent claim 31, as best understood, DeLaCruz (Fig. 5) discloses a microelectronic device comprising:
a first layer having one or more dies 506/508/510/n (¶ 0095) comprising active circuitry, the active circuitry comprising a plurality of circuit elements among the one or more dies (¶ 0074); and
a second layer 108 directly hybrid-bonded to the one or more dies (¶ 0096), the second layer 108 comprising a semiconductor material (¶ 0074) and one or more routing layers 512/514 (¶¶ 0074, 76), wherein:
the one or more dies 506/508/510/n are fabricated in a first process node (¶ 0087);
at least a portion of the second layer 108 is fabricated in a second process node (¶ 0072), the first process node being a more advanced node than the second process node (¶¶ 0072, 87); and
at least some of the one or more routing layers communicatively couple at least some of the plurality of circuit elements to one another (¶ 0079) through interconnections formed by direct hybrid bonds (¶ 0096) between the second layer and the one or more dies (¶ 0079).
The limitations “fabricated in a first process node” and “fabricated in a second process node” are product-by-process limitations that do not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 32, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 31, wherein the one or more dies 506/508/510/n comprise a first die and a second die, and wherein at least one circuit element of the first die is communicatively coupled to at least one circuit element of the second die through the interconnections formed by the direct hybrid bonds between the second layer 108 and the one or more dies (¶ 0079 - “108 uses chiplets 506 & 508 & 510 . . . n and communicatively connects them together”).
Regarding claim 33, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 32, wherein the at least one circuit element of the first die comprises a logic component (¶ 0090), and wherein the at least one circuit element of the second die comprises a memory component (¶ 0091 - “510 may be a memory device”) communicatively coupled to the logic component of the first die (¶ 0091 - “510 has multiple independent functions and multiple ports that may communicate with a plurality of functional elements”) through the interconnections formed by the direct hybrid bonds between the second layer and the one or more dies (¶ 0079).
Regarding claim 34, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 31, wherein the one or more dies 506/508/510/n comprises two or more dies in a side-by-side arrangement (Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24-26, 35, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz as applied to claims 21 and 31 above, and further in view of US 2017/0011993 A1 to Zhao et al. (hereinafter “Zhao”).
Regarding claim 24, DeLaCruz discloses the microelectronic device of claim 21, however fails to expressly disclose: wherein the substrate comprises one or more input/output (I/O) connectors that communicatively couple at least one circuit element of the plurality of dies to an external device.
In the same field of endeavor, Zhao (Fig. 4b) discloses a microelectronic device including a substrate 403 (¶ 0051) comprising one or more input/output (I/O) connectors 419/409 (¶ 0054) that communicatively couple at least one circuit element of the plurality of dies 401/431 (¶ 0051) to an external device (through 445/447; ¶ 0055). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include I/O connectors as recited above and taught in Zhao, in the microelectronic device of DeLaCruz and to connect them to an external device for the purpose of providing electrical connectivity and forming a functional microelectronic device able to be integrated with external components.
Regarding claim 25, DeLaCruz and Zhao disclose the microelectronic device of claim 24, wherein the plurality of dies 506/508/510/n is disposed on a first side (top) of the substrate 108 (DeLaCruz, Fig. 5; see also Zhao, Fig. 4b - dies 401/431 and substrate 403), wherein the one or more I/O connectors 419/409 (Zhao, Fig. 4b) comprises a plurality of interconnects disposed at a second side (bottom) of the substrate opposite the first side (top) (Zhao, Fig. 4b), and wherein the microelectronic device further comprises an interposer 445 (¶ 0055) connected to the plurality of interconnects 419/409 (Zhao, Fig. 4b).
Regarding claim 26, DeLaCruz and Zhao disclose the microelectronic device of claim 25, wherein the plurality of interconnects 419/409 comprises at least one of pillars or bumps (¶ 0054).
Regarding claim 35, DeLaCruz discloses the microelectronic device of claim 31, however fails to expressly disclose: wherein the second layer comprises one or more input/output (I/O) connectors that communicatively couple at least one circuit element of the plurality of circuit elements to an external device.
In the same field of endeavor, Zhao (Fig. 4b) discloses a microelectronic device including a second layer 403 (¶ 0051) comprising one or more input/output (I/O) connectors 419/409 (¶ 0054) that communicatively couple at least one circuit element of the plurality of circuit elements 401/431 (¶ 0051) to an external device (through 445/447; ¶ 0055). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include I/O connectors as recited above and taught in Zhao, in the microelectronic device of DeLaCruz and to connect them to an external device for the purpose of providing electrical connectivity and forming a functional microelectronic device able to be integrated with external components.
Regarding claim 36, DeLaCruz and Zhao disclose the microelectronic device of claim 35, wherein the one or more dies 506/508/510/n are disposed on a first side (top) of the second layer 108 (DeLaCruz, Fig. 5; see also Zhao, Fig. 4b - dies 401/431 and second layer 403), wherein the one or more I/O connectors 419/409 (Zhao, Fig. 4b) comprises a plurality of interconnects disposed at a second side (bottom) of the second layer opposite the first side (top) (Zhao, Fig. 4b), and wherein the microelectronic device further comprises an interposer 445 (¶ 0055) connected to the plurality of interconnects 419/409 (Zhao, Fig. 4b).
Claims 27-30 and 37-40 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz.
Regarding claim 27, DeLaCruz discloses the microelectronic device of claim 21, however, in the instant embodiment, does not expressly disclose: wherein an additional semiconductor layer is bonded over the plurality of dies. In a different embodiment, DeLaCruz (Fig. 3) discloses an additional semiconductor layer 304 (¶ 0041) bonded over the plurality of dies 306 (¶ 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an additional semiconductor layer bonded over the plurality of dies in the microelectronic device of DeLaCruz for the purpose of forming a device with desired functionality with increased signal propagation speed and reduced power consumption (¶¶ 0043-44).
Regarding claim 28, DeLaCruz discloses the microelectronic device of claim 27, wherein the additional semiconductor layer 304 (¶ 0041) comprises an application specific integrated circuit (ASIC). The limitation “comprises an application specific integrated circuit (ASIC)” is considered functional language that does not structurally distinguish the claimed invention over the prior art. DeLaCruz discloses the structure as recited in the claim as currently drafted, thus the structure of DeLaCruz is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I).
Regarding claim 29, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 21, wherein the interconnections formed by the direct hybrid bonds between the substrate 108 and the plurality of dies 506/508/510/n have a pitch between about 1 µm and about 10 µm (¶¶ 0095-96). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Regarding claim 30, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 21, wherein a spacing between an interconnection of the interconnections formed by the direct hybrid bonds between the one or more dies 506/508/510/n and the substrate 108 and a neighboring interconnection of the interconnections formed by the direct hybrid bonds between the one or more dies and the substrate is within a range from about 1 µm to about 10 µm (¶¶ 0095-96). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Regarding claim 37, DeLaCruz discloses the microelectronic device of claim 31, however, in the instant embodiment, does not expressly disclose: wherein an additional semiconductor layer is directly bonded over the one or more dies. In a different embodiment, DeLaCruz (Fig. 3) discloses an additional semiconductor layer 304 (¶ 0041) is directly bonded over the one or more dies 306 (¶ 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an additional semiconductor layer directly bonded over the one or more dies in the microelectronic device of DeLaCruz for the purpose of forming a device with desired functionality with increased signal propagation speed and reduced power consumption (¶¶ 0043-44).
Regarding claim 38, DeLaCruz discloses the microelectronic device of claim 37, wherein the additional semiconductor layer 304 (¶ 0041) comprises an application specific integrated circuit (ASIC). The limitation “comprises an application specific integrated circuit (ASIC)” is considered functional language that does not structurally distinguish the claimed invention over the prior art. DeLaCruz discloses the structure as recited in the claim as currently drafted, thus the structure of DeLaCruz is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I).
Regarding claim 39, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 31, wherein the interconnections formed by the direct hybrid bonds between the second layer 108 and the one or more dies 506/508/510/n have a pitch between about 1 µm and about 10 µm (¶¶ 0095-96). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Regarding claim 40, DeLaCruz (Fig. 5) discloses the microelectronic device of claim 31, wherein a spacing between an interconnection of the interconnections formed by the direct hybrid bonds between the one or more dies 506/508/510/n and the second layer 108 and a neighboring interconnection of the interconnections formed by the direct hybrid bonds between the one or more dies and the second layer is within a range from about 1 µm to about 10 µm (¶¶ 0095-96). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2017/0271307 A1 to Hiner et al. disclosing a semiconductor package structure connecting die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
21 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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