DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 4, claims 1-8, 13, 14) in the reply filed on 7/22/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 4, 8, 14 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2019/0269009 (Park ‘009) in view of U.S. Patent No. 9,001,300 (Kim ‘300).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Park ‘009 discloses
1. A circuit board comprising:
a plurality of insulating layers 571, 572, 573, 574, 575;
at least one conductive layer 511, 513, 515, 517, 531, 533, 535 disposed between the plurality of insulating layers 571, 572, 573, 574, 575;
a connection pad 515a, 533a disposed under the conductive layer 511, 531;
a signal line 513c, 533c disposed under the conductive layer 511, 531.
Park ‘009 fails to disclose
a signal line electrically connected to the connection pad; and
a protective layer disposed under the conductive layer and having a lower surface positioned in a same plane as a lower surface of the connection pad.
Kim ‘300 teaches (at least Figs. 5, 7B)
A circuit board comprising:
a signal line 112, 122, 123 electrically connected to the connection pad 23, 64, 66; and
a protective layer 70 disposed under the conductive layer 83, 84, 86 and having a lower surface positioned in a same plane as a lower surface of the connection pad 64, 66.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a signal line connected to a connection pad, and a protective layer positioned in a same plane as a lower surface of the connection pad in Park ‘009. The motivation would be to reduce the stepped difference at a connected portion while maintaining reliable signal connection through the connection pad, thereby providing a flat connection region as taught by Kim ‘300 (Summary).
Park ‘009 discloses
3. The circuit board of claim 1, wherein the conductive layer includes:
a first conductive layer 515 disposed on the connection pad 513a and the signal line 511c; and
a second conductive layer 517 disposed on the first conductive layer 515.
Park ‘009 discloses
4. The circuit board of claim 3, wherein the plurality of insulating layers 571, 572, 573, 574, 575 include a first insulating layer 572 disposed between the first conductive layer 515 and the connection pad 513a, the connection pad 513a is connected to the first conductive layer 515 through at least one first contact hole 551a penetrating the first insulating layer 572, and
Kim ‘300 teaches
the signal line 112 is connected to the first conductive layer 83 through at least one second contact hole 73 penetrating the first insulating layer 30.
The combination of references teaches
8. The circuit board of claim 1, wherein the conductive layer includes:
Kim ‘300 teaches
a first conductive layer 83, 84, 86 disposed on the connection pad 23, 64, 66 and the signal line 112, 122, 123;
Park ‘009 discloses
a second conductive layer 513 disposed on the first conductive layer 511; and
a third conductive layer 515 disposed on the second conductive layer 513.
Park ‘009 discloses ([0093])
14. The circuit board of claim 1, wherein each of the connection pad 515a, 533a, the signal line 513c, 533c, and the conductive layer 511, 513, 515, 517, 531, 533, 535 includes copper (Cu).
Claim(s) 2, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park ‘009 in view of Kim ‘300 as applied to claim 1 above, and further in view of CN Publication No. 104779219 (Park ‘219).
The combination of references fails to teach
2. The circuit board of claim 1, wherein a thickness of the protective layer is equal to a thickness of the connection pad.
Park ‘219 teaches
A circuit board comprising:
wherein a thickness of the protective layer 120 is equal to a thickness of the connection pad 620.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a protective layer and a connection pad having equal thickness in the modified device of Park ‘009. The motivation would be to provide a substantially planar connection surface, reduce a stepped difference, and facilitate reliable electrical connection as taught by Park ‘219.
Park ‘219 teaches
13. The circuit board of claim 1, wherein the protective layer 120 includes a solder resist.
Claim(s) 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park ‘009 in view of Kim ‘300 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2010/0052993 (Kim ‘993).
The combination of references fails to teach
5. The circuit board of claim 4, wherein the first conductive layer includes a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction crossing the first direction, and wherein the second conductive layer has a plate shape.
Kim ‘993 teaches
A circuit board comprising:
wherein the first conductive layer includes a plurality of conductive patterns 130 each extending in a first direction and spaced apart from each other in a second direction crossing the first direction, and wherein the second conductive layer 140 has a plate shape.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide first conductive layer including a plurality of conductive patterns and a second conductive layer having a plate shape in the modified device of Park ‘009. The motivation would be to reduce dispersion, noise, and crosstalk and improve the quality of signal transmission as taught by Kim ‘993 ([0053]-[0058]).
Park ‘009 discloses
6. The circuit board of claim 5, wherein the connection pad 515a, 533a and the signal line 513c, 533c are spaced apart from each other in the first direction, and wherein each of the conductive patterns (Kim ‘003) overlaps the connection pad 515a, 533a and the signal line 513c, 533c in a plan view.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park ‘009 in view of Kim ‘300 as applied to claim 1 above, and further in view of U.S. Patent No. 6,757,217 (Jochym).
The combination of references fails to teach
7. The circuit board of claim 4, wherein each of the first contact hole and the second contact hole has a polygonal cross-sectional shape.
Jochym teaches
A circuit board comprising:
wherein each of the first contact hole and the second contact hole has a polygonal cross-sectional shape 405 (column 4, lines 15-56).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a contact hole with a polygonal cross-sectional shape in the modified device of Park ‘009. The motivation would be to provide reliable electrical contact between conductive layers of a circuit board based on engineering design considerations as taught by Jochym. See MPEP 2144.04.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2020/0084899 (Kang), 2020/0022261 (Choi), 2009/0166892 (Lee), 2004/0223309 (Haemer) teach a circuit board for use with a display device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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