CTNF 18/418,035 CTNF 98637 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicants’ election without traverse of Invention I, claims 1-14, in the reply filed on 23 April 2026 is acknowledged. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. The restriction requirement is deemed proper and made final. Response to Amendment The Office acknowledges receipt on 24 April 2026 of Applicant’s amendments in which claims 15-20 are cancelled and claims 21-26 are newly added. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Claim 5, lines 2 and 3, recites “a deep contact extending from the interconnect structure, through the semiconductor substrate and the first dielectric layer,” which is not illustrated by the drawings. Instead, for example, Figs. 13, 14, and 27 illustrates the deep contact (234) extends from the interconnect structure (240) through the first dielectric layer (212) and terminates at a top surface of the semiconductor substrate (202), without penetrating the semiconductor substrate (202). 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections 07-29-01 AIA Claim 12 is objected to because of the following informalities: Claim 12, lines, recites “a plurality of deep contact,” which should read “a plurality of deep contacts” for proper grammar and composition . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 21, line 3, recites “the substrate,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the first substrate.” Claims 22-26 are rejected due to their dependence from base claim 21. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 21, 22, and 24-26 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Miyazaki et al. (US20220352226A1) . Regarding claim 21, as interpreted in view of the indefiniteness rejection, Miyazaki teaches in Fig. 75 a semiconductor device structure, comprising: a first substrate (100S) comprising a plurality of photodiodes (PD) {[0404]}; a plurality of transfer gate transistors (TR) disposed over the first substrate (100S) {[0404]}; a first passivation layer (122) over the first substrate (100S) and the plurality of transfer gate transistors (TR) {[0425]}; a second substrate (200S) disposed over the first passivation layer (122) and comprising an isolation structure (212) {[0430]}; a second passivation layer (221) over the second substrate (200S) {[0451]}; a deep contact (TGV) extending continuously through the second passivation layer (221), the isolation structure (212), and the first passivation layer (122) {[0430]}; and an interconnect structure (W1-W4) disposed over the second passivation layer (221) {[0451]}. Regarding claim 22, Miyazaki teaches in Fig. 75 the semiconductor device structure of claim 21, and Miyazaki further teaches further comprising: a plurality of source follower transistors (210:AMP), a plurality of row select transistors (210:SEL) and a plurality of reset transistors (210:RST) disposed over the second substrate (200S) {[0394, 0396]}. Regarding claim 24, Miyazaki teaches in Fig. 75 the semiconductor device structure of claim 21, and Miyazaki further teaches wherein the plurality of photodiodes (PD) are at least partially spaced apart from one another laterally by a deep trench isolation feature (117) {[0405]}. Regarding claim 25, Miyazaki teaches in Fig. 75 the semiconductor device structure of claim 24, and Miyazaki further teaches wherein the deep trench isolation feature (117) comprises a metal liner (117A) and a dielectric fill material (117B) {[0406]}. Regarding claim 26, Miyazaki teaches in Fig. 75 the semiconductor device structure of claim 25, and Miyazaki further teaches wherein the metal liner (117A) comprises aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu) {[0406], tungsten} . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki as applied to claim 22 above, and further in view of Huang et al. (US20230207587A1) . Regarding claim 23, Miyazaki teaches in Fig. 75 the semiconductor device structure of claim 22, and Miyazaki further teaches wherein each of the plurality of transfer gate transistors (TR) comprises a first channel area (implicit), each of the plurality of source follower transistors (AMP) comprises a second channel area (implicit), each of the plurality of row select transistors (SEL) comprises a third channel area (implicit), and each of the plurality of reset transistors (RST) comprises a fourth channel area (implicit). Miyazaki does not teach the second channel area is greater than the first channel area, the third channel area or the fourth channel area. Huang teaches in Fig. 2 and paragraph [0031] a second channel area (area of 210) [of a source follower transistor] is greater than a first channel area (area of 204) [of a transfer transistor], a third channel area (area of 212) [of a row select transistor] or a fourth channel area (area of 208) [of a reset transistor]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the teachings of Huang, to achieve the above identified subject matter, for reducing RTS noises . Huang [0036] . 07-21-aia AIA Claim (s) 1, 4-6, 10, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang . Regarding claim 1, Miyazaki teaches in Fig. 4 an image sensor structure, comprising: a semiconductor substrate (11) comprising a photodiode (41) {[0169]}; a transfer gate transistor (TR) disposed over the semiconductor substrate (11) and comprising a first channel area (implicit) {Fig. 4; [0162]}; a first insulator layer (46) disposed over the semiconductor substrate (11) {e.g., Fig. 4; [0169]}; a semiconductor layer (e.g., lower portion of 21) disposed over the first insulator layer (46) {e.g., Fig. 4; [0169]}; a source follower transistor (AMP) disposed over the semiconductor layer (e.g., lower portion of 21) and comprising a second channel area (implicit) {e.g., Fig. 6; [0180]}; a row select transistor (SEL) disposed over the semiconductor layer (e.g., lower portion of 21) and comprising a third channel area (implicit) {e.g., Fig. 6; [0180]}; and a reset transistor (RST) disposed over the semiconductor layer (e.g., lower portion of 21) and comprising a fourth channel area {e.g., Fig. 6; [0180]}. Miyazaki does not expressly teach in the embodiment of Fig. 4 the first insulator layer is a dielectric. However, Miyazaki teaches an insulator layer 1512 made of a dielectric (SiO2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the further teachings of Miyazaki – such that the first insulator layer is a dielectric – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Miyazaki does not teach the second channel area is greater than the first channel area, the third channel area or the fourth channel area. In an analogous art, Huang teaches in Fig. 2 and paragraph [0031] a second channel area (area of 210) [of a source follower transistor] is greater than a first channel area (area of 204) [of a transfer transistor], a third channel area (area of 212) [of a row select transistor] or a fourth channel area (area of 208) [of a reset transistor]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the teachings of Huang, to achieve the above identified subject matter, for reducing RTS noises . Huang [0036]. Regarding claim 4, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, and Miyazaki further teaches further comprising: a second dielectric layer (52) over the source follower transistor (AMP), the row select transistor (SEL), and the reset transistor (RST) {Fig. 4; [0174]}; and an interconnect structure (56) over the second dielectric layer (52) {Fig. 4; [0174]}. Regarding claim 5, Miyazaki as modified by Huang teaches the image sensor structure of claim 4, and Miyazaki further teaches further comprising: a deep contact (54, FD) extending from the interconnect structure (56), through the semiconductor substrate (11) and the first dielectric layer (modified 46) {Fig. 4; [0164, 0172]}. Regarding claim 6, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, and Miyazaki further teaches further comprising: a deep trench isolation feature (43) disposed adjacent the photodiode (41) {Fig. 4; [0169, 0170]}. Regarding claim 10, Miyazaki teaches in Figs. 1 and 4 a semiconductor device structure, comprising: a substrate (11) comprising a plurality of photodiodes (41) {[0169]}; a plurality of transfer gate transistors (TR) disposed over the substrate (11) {Fig. 4; [0162]}; a first insulator layer (46) over the substrate (11) and the plurality of transfer gate transistors (TR) {e.g., Fig. 4; [0169]}; a semiconductor layer (e.g., lower portion of 21) disposed over the first insulator layer (46) {e.g., Fig. 4; [0169]}; a plurality of source follower transistors (AMP), a plurality of row select transistors (SEL) and a plurality of reset transistors (RST) disposed over the semiconductor layer (e.g., lower portion of 21) {e.g., Fig. 6; [0180]}; a second dielectric layer (52) over the plurality of source follower transistors (AMP), the plurality of row select transistors (SEL) and the plurality of reset transistors (RST) {Fig. 4; [0174]}; and an interconnect structure (56) disposed over the second dielectric layer (52) {Fig. 4; [0174]}, wherein each of the plurality of transfer gate transistors (TR) comprises a first channel area (implicit), each of the plurality of source follower transistors (AMP) comprises a second channel area (implicit), each of the plurality of row select transistors (SEL) comprises a third channel area (implicit), and each of the plurality of reset transistors (RST) comprises a fourth channel area (implicit) {Fig. 4; [0174]}. Miyazaki does not expressly teach in the embodiment of Fig. 4 the first insulator layer is a dielectric. However, Miyazaki teaches an insulator layer 1512 made of a dielectric (SiO2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s semiconductor device structure based on the further teachings of Miyazaki – such that the first insulator layer is a dielectric – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Miyazaki does not teach the second channel area is greater than the first channel area, the third channel area or the fourth channel area. In an analogous art, Huang teaches in Fig. 2 and paragraph [0031] a second channel area (area of 210) [of a source follower transistor] is greater than a first channel area (area of 204) [of a transfer transistor], a third channel area (area of 212) [of a row select transistor] or a fourth channel area (area of 208) [of a reset transistor]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s semiconductor device structure based on the teachings of Huang, to achieve the above identified subject matter, for reducing RTS noises . Huang [0036]. Regarding claim 12, Miyazaki as modified by Huang teaches the semiconductor device structure of claim 10, and Miyazaki further teaches further comprising: a plurality of deep contact[s] (54, FD) continuously extending through the first dielectric layer (modified 46), the semiconductor layer (e.g., lower portion of 21) and the second dielectric layer (52) {Fig. 4; [0164, 0172]}. Regarding claim 13, Miyazaki as modified by Huang teaches the semiconductor device structure of claim 10, and Miyazaki further teaches wherein the plurality of photodiodes (41) are at least partially spaced apart from one another by a deep trench isolation feature (43) {Fig. 4; [0169, 0170]} . 07-22-aia AIA Claim (s) 2, 3, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang as applied to claim 1 (for claims 2 and 3) and claim 10 (for claim 11) above, and further in view of Gao et al. (US20230013187A1) . Regarding claim 2, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, but Miyazaki does not teach wherein a ratio of the second channel area to the first channel area is greater than 1.2. In an analogous art, Gao in paragraphs [0033, 0034] that: (1) random telegraph signal (RTS) noise is inversely proportional to the channel area of a source follower and (2) such RTS noise adversely affects low-light performance. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor as modified by Huang based on the teachings of Gao for discovering an optimum or workable range of RTS noise and/or low-light performance – such that a ratio of the second channel area [of a source follower transistor] to the first channel area [of a transfer transistor] is greater than 1.2 – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation . MPEP §2144.05(II)(A). Regarding claim 3, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, but Miyazaki does not teach wherein the second channel area is greater than a sum of the third channel area and the fourth channel area. Gao in paragraphs [0033, 0034] that: (1) random telegraph signal (RTS) noise is inversely proportional to the channel area of a source follower and (2) such RTS noise adversely affects low-light performance. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor as modified by Huang based on the teachings of Gao for discovering an optimum or workable range of RTS noise and/or low-light performance – such that the second channel area [of a source follower transistor] is greater than a sum of the third channel area [of a row select transistor] and the fourth channel area [of a reset transistor] – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation . MPEP §2144.05(II)(A). Regarding claim 11, Miyazaki as modified by Huang teaches the semiconductor device structure of claim 10, but Miyazaki does not teach wherein a ratio of the second channel area to the first channel area is greater than 1.2. In an analogous art, Gao in paragraphs [0033, 0034] that: (1) random telegraph signal (RTS) noise is inversely proportional to the channel area of a source follower and (2) such RTS noise adversely affects low-light performance. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s semiconductor device structure as modified by Huang based on the teachings of Gao for discovering an optimum or workable range of RTS noise and/or low-light performance – such that a ratio of the second channel area [of a source follower transistor] to the first channel area [of a transfer transistor] is greater than 1.2 – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation . MPEP §2144.05(II)(A) . 07-22-aia AIA Claim (s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang as applied to claim 1 above, and further in view of Huang et al. (US20200411585A1) . Regarding claim 7, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, but Miyazaki does not teach wherein the source follower transistor, the row select transistor and the reset transistor are planar transistors. In an analogous art, Huang ‘585 teaches in paragraph [0059] a source follower transistor, a row select transistor and a reset transistor may be planar transistors or alternatively may be non-planar transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the teachings of Huang, to achieve the above identified subject matter, because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp . MPEP §2143((I)(E). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Furthermore, all the claimed elements (e.g., transistors, planar) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Huang ‘585) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A) . 07-22-aia AIA Claim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang as applied to claim 1 above, and further in view of Huang ‘585 and Fossum et al. (US20240213289A1) . Regarding claim 8, Miyazaki as modified by Huang teaches the image sensor structure of claim 1, but Miyazaki does not teach wherein the row select transistor and the reset transistor comprise planar transistors, wherein the source follower transistor comprises a multi-gate transistor. Huang ‘585 teaches in paragraph [0059] a row select transistor and a reset transistor may be planar transistors or alternatively may be non-planar transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the teachings of Huang, to achieve the above identified subject matter, because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp . MPEP §2143((I)(E). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Furthermore, all the claimed elements (e.g., transistors, planar) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Huang ‘585) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). In an analogous art, Fossum teaches in paragraph [0047] a source follower transistor comprises a multi-gate transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor based on the teachings of Huang, to achieve the above identified subject matter, to achieve a low 1/f noise … while reducing the FD node parasitic capacitance significantly . Fossum [0047]. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Furthermore, all the claimed elements (e.g., multi-gate transistor) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Fossum) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A) . 07-22-aia AIA Claim (s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang, Huang ‘585, and Fossum as applied to claim 8 above, and further in view of Kao et al. (US20220278144A1) . Regarding claim 9, Miyazaki as modified by Huang teaches the image sensor structure of claim 8, but Miyazaki does not teach wherein the source follower transistor comprises a channel region and a gate structure, wherein the gate structure engages more than one side of the channel region. In an analogous art, Kao teaches in paragraph [0016] a multi-gate transistor having a channel region and a gate structure that engages more than one side of the channel region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s image sensor as modified by Huang and Fossum based on the teachings of Kao – such that Fossum’s source follower transistor comprises a channel region and a gate structure, wherein the gate structure engages more than one side of the channel region – to achieve a low 1/f noise … while reducing the FD node parasitic capacitance significantly . Fossum [0047]. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Furthermore, all the claimed elements (e.g., multi-gate transistor, channel sides) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kao) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A) . 07-22-aia AIA Claim (s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Huang as applied to claim 13 above, and further in view of Phan et al. (US20250081656A1) . Regarding claim 14, Miyazaki as modified by Huang teaches the semiconductor device structure of claim 13, and Miyazaki further teaches wherein the deep trench isolation feature (43) comprises a metal liner and a dielectric fill material (SiO2) {[0170]}. Miyazaki does not teach the deep trench isolation feature comprises a metal liner. In an analogous art, Phan teaches in Fig. 2A and paragraph [0040] a deep trench isolation feature (206, 207) comprises a metal liner (207) and a dielectric fill material (206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyazaki’s semiconductor device structure as modified by Huang based on the teachings of Phan, to achieve the above identified subject matter, to provide surface passivation . Phan [0040]. Moreover, all the claimed elements (e.g., deep trench isolation feature, metal liner) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Phan) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yang et al. (US20220068721A1) teaches a semiconductor device includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.W.W./Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891 Application/Control Number: 18/418,035 Page 2 Art Unit: 2891 Application/Control Number: 18/418,035 Page 3 Art Unit: 2891 Application/Control Number: 18/418,035 Page 4 Art Unit: 2891 Application/Control Number: 18/418,035 Page 5 Art Unit: 2891 Application/Control Number: 18/418,035 Page 6 Art Unit: 2891 Application/Control Number: 18/418,035 Page 7 Art Unit: 2891 Application/Control Number: 18/418,035 Page 8 Art Unit: 2891 Application/Control Number: 18/418,035 Page 9 Art Unit: 2891 Application/Control Number: 18/418,035 Page 10 Art Unit: 2891 Application/Control Number: 18/418,035 Page 11 Art Unit: 2891 Application/Control Number: 18/418,035 Page 12 Art Unit: 2891 Application/Control Number: 18/418,035 Page 13 Art Unit: 2891 Application/Control Number: 18/418,035 Page 14 Art Unit: 2891 Application/Control Number: 18/418,035 Page 15 Art Unit: 2891 Application/Control Number: 18/418,035 Page 16 Art Unit: 2891
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