DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species (b), (claims 1-11), in the reply filed on 07/22/2026 is
acknowledged. Claims 12-25 are withdrawn by consideration.
Regarding the Applicant’s election with traverse, the Species are independent or distinct because include mutually exclusive characteristics such as: “add tungsten to the etching gas before etching a low k-region and remove tungsten from the etching gas after penetrating the low-k region”(Species (a)), “extending, with an etch process, the opening through the semiconductor substrate”(Species (b)), “form a tungsten nitride on the first sidewalls of the nitride layer before or during etching of the silicon containing layer”(Species (c)), “extending the opening through the mask layer and the semiconductor substrate”(Species (d)).
Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Claim Rejections - 35 USC § 112
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being
incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: The claims lack structural relationship between the low-k region and the substrate is not specified so its unclear where this low-k region exists. For the examination purpose and according to figures 4A-4D, the lack of structural relationship between the low-k region and the substrate is interpreted as a low-k region on the surface of the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jayanti et al. (US 20250308919 A1, hereinafter Jayanti) in view of Wang et al. (US 20030173333 A1, hereinafter Wang).
Re: Independent Claim 1, Jayanti discloses a process comprising:
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Jayanti’s Figure 2B-Annotated.
forming a nitride layer (204 single etch layer of silicon nitride in [0025], Figs. 2A-2C) over a semiconductor substrate (202 in [0025], Figs. 2A-2C);
forming a mask layer (208 mask in [0025], Figs. 2A-2C) over the nitride layer (204);
creating an opening (220 opening in Figs. 2A-2B) through the mask layer (208) and the nitride layer (204);
exposing the nitride layer (204) to an etch gas comprising tungsten (an etch gas comprising tungsten hexafluoride in [0026-0028]); and
extending, with an etch process (the metal containing passivation layer 224 to be deposited on locations of the sidewalls of the etch features 220 in [0026-0028], Figs. 2A-2C), the opening (220).
Jayanti does not expressly disclose extending, with an etch process, the opening through the semiconductor substrate.
However, in the same manufacturing of a semiconductor device field of endeavor, Wang discloses extending, with an etch process (a small amount of substrate 36 is etched in [0039], Figs. 3a-3e), the opening (44 an opening extending through the substrate 36 in [0039], Figs. 3a-3e) through the semiconductor substrate (36 in [0039], Figs. 3a-3e).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Wang’s method of extending, with an etch process, the opening through the semiconductor substrate to Jayanti’s method in order to have the predictable result of using the etching process of Jayanti in an application which requires an opening in a substrate ([0002], Wang) which uses an etch feature less subject to bowing ([0024], Jayanti).
Re: Claim 2, Jayanti modified by Wang discloses the process of claim 1, wherein the etch gas comprises tungsten hexafluoride (WF6) (an etch gas comprising tungsten hexafluoride in [0026-0028], Jayanti).
Re: Claim 3, Jayanti modified by Wang discloses the process of claim 2,
Jayanti modified by Wang does not expressly disclose after etching of a low-k region and during etching of the semiconductor substrate, the tungsten hexafluoride (WF6) is removed from the etch gas.
However, in the same manufacturing of a semiconductor device field of endeavor, Wang discloses a low-k region (34 a silicon dioxide layer as a top region of the substrate 36 in [0039], Figs. 3a-3e) included in the semiconductor substrate (36 in [0039], Figs. 3a-3e).
Therefore, Jayanti in view of Wang teaches after etching of a low-k region (34, Wang) and during etching of the semiconductor substrate (36, [0039], Wang), the tungsten hexafluoride (WF6) is removed from the etch gas (near the end of the etch process, the flow rate of the WF6 is ramped down in [0029], Jayanti).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s low-k region to Jayanti’s substrate to obtain a method for etching substrates having a low-k region ([0002], Wang).
Re: Claim 4, Jayanti modified by Wang discloses the process of claim 1, wherein the etch gas further comprises a halogen (etch gas comprising halogen in [0019], Jayanti).
Re: Claim 5, Jayanti modified by Wang discloses the process of claim 4, wherein the etch gas further comprises nitrogen (NO2, NO3 in [0019], Jayanti).
Re: Claim 7, Jayanti modified by Wang discloses the process of claim 4, wherein the nitride layer (204, Jayanti) is exposed to the etch gas prior to etching of a low-k region of the semiconductor substrate (simultaneous etching 204 and deposition of a metal passivation layer 224 provides a faster etching process and faster throughput in [0028], Jayanti).
Re: Claim 8, Jayanti modified by Wang discloses the process of claim 7, wherein the nitride layer (204, Jayanti) is exposed to the etch gas during etching of the low-k region (Wang’s method of substrate etch applied to Jayanti’s method, results in simultaneous etching 204 and Wang’s substrate while a metal passivation layer 224 is deposited in [0028], Jayanti).
Re: Claim 9, Jayanti modified by Wang discloses the process of claim 1, further comprising: forming a layer of tungsten nitride over sidewalls of the nitride layer (tungsten nitride in [0028], Fig. 2B, Jayanti).
Re: Claim 10, Jayanti modified by Wang discloses the process of claim 1, wherein the etch
process further comprises repeating the following steps: etching using the etch gas for a first duration (simultaneous etching 204 and deposition of a metal passivation layer 224 in [0028], Jayanti),
Jayanti modified by Wang does not expressly disclose an etch process further comprises passivating using a polymer depositing gas for a second duration.
However, in the same manufacturing of a semiconductor device field of endeavor, Wang disclose a passivating using a polymer depositing gas (a process gas comprising, for example, carbon tetrafluoride CF4 to form a thin coating 42 of polymer in [0039], Figs 3a-3e) for a second duration (after etching layer 34, a thing coating layer of polymer is deposited on the sidewalls to cover and passivate the sidewall silicon surface in [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s method of a passivating using a polymer depositing gas for a second duration to the combination of Jayanti and Wang to cover and passivate the sidewall of the etched surface ([0039], Wang).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jayanti et al. (US 20250308919 A1, hereinafter Jayanti) in view of Chang et al. (US 20210391181 A1, hereinafter Chang).
Re: Claim 6, Jayanti modified by Wang discloses the process of claim 4,
Jayanti modified by Wang does not expressly disclose wherein the etch gas further comprises silicon tetrafluoride (SiF4).
However, in the same manufacturing of a semiconductor device field of endeavor, Chang discloses wherein the etch gas further comprises silicon tetrafluoride (SiF4) (one of the etch gas includes silicon tetrafluoride to form a protective layer 250 in [0052]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Chang’s method of wherein the etch gas further comprises silicon tetrafluoride (SiF4) to the combination of Jayanti and Wang in order to have the predictable result of forming a protective layer in an etch process ([0052], Chang).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jayanti in view of Wang and further in view of Kim et al. (US 20220375759 A1, hereinafter Kim).
Re: Claim 11, Jayanti modified by Wang discloses the process of claim 1,
Jayanti modified by Wang does not expressly disclose wherein the etch process further comprises: continuously etching using the etch gas with an anisotropic etch process.
However, in the same manufacturing of a semiconductor device field of endeavor, Kim discloses wherein the etch process further comprises: continuously etching using the etch gas with an anisotropic etch process (performing a plurality of cycles of the cyclic etch process corresponding to an anisotropic plasma etch process, a plasma-off passivation step, and a plasma-on passivation step in [0042]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kim’s method of wherein the etch process further comprises: continuously etching using the etch gas with an anisotropic etch process to the combination of Jayanti and Wang in order to have the predictable result of improving the etch resistivity of a passivation layer and/or ensuring the coverage of the entire recess by the passivation layer ([0042], Kim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tokashiki (US 10903109 B2) teaches “METHODS OF FORMING HIGH ASPECT RATIO OPENINGS AND METHODS OF FORMING HIGH ASPECT RATIO FEATURES”. This document is related to some methods of forming high aspect ratio openings and forming a protective material on sidewalls of the dielectric material.
Nguyen (US 20060276033 A1) teaches “ADHESION OF TUNGSTEN NITRIDE FILMS TO A SILICON SURFACE”. This document is related to a process to form a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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