DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on February 9, 2026.
Claim 1 is amended. Claims 3-4 are canceled. No claims are added.
Response to Arguments
3. Applicant’s arguments, see page 3, filed February 9, 2026, with respect to claim 1, have been fully considered and are persuasive. Therefore, the 35 USC § 103 rejection of claim 1 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, et al (US 20150325300 A1).
Applicant correctly asserts the limitation, “without coupling the erase gate line to other rows in the array,” as recited in amended claim 1, is not disclosed in Auclair (US 7437631 B2) and Seo (US 20130223148 A1). This limitation specifically addresses the architecture of Seo. Both Applicant and Seo utilize erase gate enable transistors to allow for erasing small sections of memory. However, Seo’s erase gate transistors are limited to distributing the erase gate line on a “sector” (analogous to Applicant’s “page”) basis. To enable erasing on a “sub-sector” (analogous to Applicant’s “word”) basis, Seo enables and inhibits cell erasure by applying appropriate voltages to the respective memory cell control gates. However, the erase gates for memory cells in adjacent rows within each sector remain electrically coupled to one another.
In contrast, Applicant’s additional erase gate enable transistors within a page (like Seo’s “sector”) electrically isolate one row’s erase gates from erase gates in other rows. In this way, Applicant’s architecture and method for erasing words/sub-sectors are distinct from Seo’s. Therefore, in light of amended claim 1, the 35 USC § 103 rejection set forth in the previous action is withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, et al (US 20150325300 A1).
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al (US 20150325300 A1), hereinafter Kim, in view of Seo, et al (US 20130223148 A1), hereinafter Seo.
Regarding independent claim 1, Kim teaches a method comprising:
erasing at the same time a word (referencing FIG. 2, ¶ [0009] teaches, e.g., “cells in sector 150 are erased by erase gate line 155”; ¶ [0007] teaches “all flash memory cells within a particular sector are erased at the same time”) of non-volatile memory cells in an array of non-volatile memory cells (FIG. 2; ¶ [0007]) arranged into rows and columns (FIG. 2, rows of cells coupled to word lines 151, 152, etc., and columns of cells coupled to bit lines 101-103), each non-volatile memory cell comprising a word line terminal (FIG. 1, WL 8), a bit line terminal (FIG. 1, BL 9), and an erase gate terminal (FIG.1, EG 6), wherein each row comprises a plurality of words of non-volatile memory cells and each word can be coupled to an erase gate line not shared with other words in the row (¶ [0008] teaches “each sector can include any number of rows and columns of flash memory cells.” ¶ [0007] teaches “flash memory cells within a particular sector share an erase gate control line.” Together, it may be understood that Kim’s “sectors” may be arranged in a row as illustrated in Figure A, with two words of 1x4 cells (i.e., one row by four columns of cells), each coupled to an erase gate control line not shared with one another. In this arrangement, Kim’s “sectors” are analogous to Applicant’s “words.”)
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Figure A: Two 1x4 sectors of Kim arranged in a row.
Kim does not teach an erase gate line is not shared with other words in the row by turning on an erase gate enable transistor to couple an erase gate line to erase gate terminals of the word of non-volatile memory cells without coupling the erase gate line to other rows in the array.
Seo teaches in FIG. 13 and ¶ [0050] a plurality of non-volatile cells arranged in “sectors” utilizing erase gate enable transistors (see blocks SSC1..SSCn) that may provide an erase gate voltage to a selected sector of cells when turned on by sector selecting lines (SSL1, SSL2).
Kim as modified by Seo applies Seo’s erase gate enable transistors (Seo FIGS. 13, 15) to the “row of sectors” structure of Kim in Figure A to create the structure of Figure B. That is, Kim as modified by Seo teaches each row comprises a plurality of words of non-volatile memory cells and erase gate selections transistors (Figure B, the row of WL2 shows two 1x4 “words,” one in Sector 3 (selected by Q3) and the other in Sector 4 (selected by Q4), and the row of WL1 shows two 1x4 “words,” one in Sector 1 (selected by Q1) and the other in Sector 2 (selected by Q2)).
Kim as modified by Seo further teaches each word can be coupled to an erase gate line not shared with other words in the row (Referencing Figure B, if SSL1 enables Q1 while SSL2 disables Q2, erase gate line EGL_S1 is shared only by the word of memory cells coupled to the row of WL1 within Sector 1, and is not shared by the word of memory cells coupled to the row of WL1 within Sector 2), by turning on an erase gate enable transistor to couple an erase gate line to erase gate terminals of the word of non-volatile memory cells (Seo ¶ [0050] teaches the erase gate voltage may be selectively provided to the erase gates of a subset of cells in an array by turning on one or more transistors in blocks SSCn; FIGS. 13, 15; Figure B, transistors Q1..Q4) without coupling the erase gate line to other rows in the array (Seo FIG. 15 and ¶ [0054] teach EGL assigned to Sectors 3 and 4 is distinct from EGL assigned to Sectors 1 and 2; therefore, as shown Figure B, the erase gate line (EGL2) of sectors 3 and 4 cannot be coupled to the row of WL1, and the erase gate line (EGL1) of sectors 1 and 2 cannot be coupled to the row of WL2).
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Figure B: Kim as modified by Seo
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Seo into the method of Kim to include turning on erase gate enable transistor(s) to selectively provide the erase gate voltage to a subset of cells in an array. The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of selectively enabling the erase operation in a subset of cells within the array (Seo ¶ [0050]).
Regarding claim 2, Kim as modified by Seo teaches the limitations of claim 1.
Kim further teaches the non-volatile memory cells are split-gate flash memory cells (FIG. 1, 10; ¶ [0003]).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827