DETAILED ACTION
This action is responsive to the Response to Election filed October 8, 2025. Claims 17-36 are pending. Claims 21-36 are new. Claims 1-16 are cancelled. Claims 17, 21, and 27 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 22, 2024. This IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of Group II (Claims 17-20) in the reply filed on October 8, 2025, is acknowledged. Claims 1-16 were cancelled by applicant and thus are not under consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GAA SRAM cell pair with backside power and bitline.
The disclosure is further objected to because of the following informalities:
In para. 24-26, Figs. 2A and 2B are referenced but those figures are not included in the drawings. It appears that some of the features and elements disclosed in these paragraphs may be intended to be part of Fig. 2 and Fig. 3. Appropriate correction is required to ensure that all features and elements disclosed in the specification are consistent with and represented in the drawings as per MPEP 608.02(d) and 37 CFR 1.83(a).
Para. 64 and 66 appear to have an inadvertent typographical error “jop”. It is believed that applicant meant “jog”. Clarification of the term or correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18, and 20-29 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara”), in view of Wang (US 20190386062) as supported by Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen”).
Regarding independent claim 17, Fujiwara discloses a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell over a substrate, wherein the first and second SRAM cells are arranged along a first direction in a top view (Fig. 7 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a front-side interconnection structure over a frontside of the substrate, wherein the front-side interconnection structure comprises:
a first word line and a second word line extending along the first direction and respectively coupled to the first and second SRAM cell (Fig. 7 where it illustrates the layout for a first and second word line WL0 and WL1 in a first direction (Y) and coupled to the first and second SRAM cell respectively);
and a first bit line extending along a second direction different from the first direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the layout for the bit line BL extending in a second direction and coupled to the first and second SRAM cells);
wherein the back-side interconnection structure comprises a second bit line extending along the second direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the second bit line BLB extending in the second direction and coupled the first and second SRAM cells).
Fujiwara is silent with respect to the bit line being on the back side.
However, Wang teaches and forming a back-side interconnection structure over a backside of the substrate (para. 94; "the second bit line in a back side interconnect layer below the device layer". Additionally, Chen specifically teaches the technology and methodology used for GAA SRAM backside signal routing and the benefits thereof.)
Fujiwara and Wang as supported by Chen are from the same field of endeavor as applicant’s invention directed to memory device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside power and bit lines on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 18, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 17.
As applied, Fujiwara further discloses further comprising:
prior to forming the front-side interconnection structure, forming a frontside contact over source/drain structures of first pass-gate transistors of the first and second SRAM cells (Fig. 6 where it illustrates source and drain contacts. It is well understood in the art that the contact layer is necessarily formed before the upper interconnect layers).
Regarding claim 20, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 17.
As applied, Wang as supported by Chen further disclose wherein
the first bit line vertically overlaps the second bit line (Fig. 4C where it illustrates a first bit line 460 vertically above the second bit line 456. It is noted that the split bit line configuration - specifically partitioning one to the frontside and one to the backside - is well understood in the art as a cornerstone of backside power delivery network (BSPDN) integration with backside signals as supported by Chen. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the bit lines of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Chen (col. 1, sect. I - Introduction and Fig. 1 for example).The resulting physical layout directly below the frontside bit line is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting standard cell height requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods.)
Regarding independent claim 21, Fujiwara discloses a method, comprising:
forming a device layer comprising a first static random access memory (SRAM) cell and a second SRAM cell arranged along a first direction in a top view (Fig. 7 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a first word line extending along the first direction and electrically coupled to the first SRAM cell (Fig. 7 where it illustrates the layout for a first word line WL0 in a first direction (Y) and coupled to the first SRAM cell respectively);
forming a second word line extending along the first direction and electrically coupled to the second SRAM cell (Fig. 7 where it illustrates the layout for second word line WL1 in a first direction (Y) and coupled to the second SRAM cell respectively);
forming a first bit line over a frontside of the device layer, wherein the first bit line extends along a second direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the layout for the bit line BL extending in a second direction (X in this case) and coupled to the first and second SRAM cells),
and the second direction is different from the first direction in the top view (Fig. 7 where it illustrates the first direction in Y and the second direction in X);
wherein the second bit line extends along the second direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the second bit line BLB extending in the second direction and coupled the first and second SRAM cells).
Fujiwara is silent with respect to the bit line being on the back side.
However, Wang teaches and forming a second bit line over a backside of the device layer (para. 94; "the second bit line in a back side interconnect layer below the device layer". Additionally, Chen specifically teaches the technology and methodology used for GAA SRAM backside signal routing and the benefits thereof),
Fujiwara and Wang as supported by Chen are from the same field of endeavor as applicant’s invention directed to memory device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside power and bit lines on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 22, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 21.
As applied, Wang further discloses wherein the first bit line vertically overlaps the second bit line (Fig. 4C where it illustrates a first bit line 460 vertically above the second bit line 456. It is noted that the split bit line configuration - specifically partitioning one to the frontside and one to the backside - is well understood in the art as a cornerstone of backside power delivery network (BSPDN) integration with backside signals as supported by Chen. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the bit lines of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Chen (col. 1, sect. I - Introduction and Fig. 1).The resulting physical layout directly below the frontside bit line is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting standard cell height requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods).
Regarding claim 23, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 21.
As applied, Fujiwara further discloses wherein the first and second word lines are over the frontside of the device layer (Fig. 7 where it illustrates a first word line WL0 and a second word line WL1 as an M2 line over the frontside).
Regarding claim 24, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 21.
As applied, Fujiwara further discloses further comprising:
forming a third word line extending along the first direction; and forming a fourth word line extending along the first direction (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where word line WL[2] and WL[3] would be the third and fourth word lines for example),
wherein the device layer further comprises a third SRAM cell and a fourth SRAM cell (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where the pair of cells 410 and 450 in position 3B would be the third and fourth SRAM cells for example),
the third and fourth SRAM cells are respectively electrically coupled to the third and fourth word lines (Fig. 9 (see configuration description above)).
and each of the third and fourth SRAMs cells is electrically coupled to the first bit line and the second bit line (Fig. 9 where BL[2] and BLB[2] are the first and second bit lines for example).
Regarding claim 25, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 21.
As applied, Fujiwara further discloses further comprising:
forming a third bit line extending along the second direction; and forming a fourth bit line extending along the second direction (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where bit lines BL[1] and BLB[1] would be the third and fourth bit lines for example),
wherein the device layer further comprises a fifth SRAM cell and a sixth SRAM cell, (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where the pair cells 401 and 450 in position 2A would be the fifth and sixth SRAM cells for example),
the fifth and sixth SRAM cells are respectively electrically coupled to the first and second word lines (Fig. 9 where WL[5] and WL[4] are the first and second word lines for example),
and each of the fifth and sixth SRAM cells is electrically coupled to the third bit line and the fourth bit line (Fig. 9 (see configuration description above)).
Regarding claim 26, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 21.
As applied, Fujiwara further discloses wherein a length of the first SRAM cell measured along the first direction is less than a length of the first SRAM cell measured along the second direction in the top view (Fig. 7 where it illustrates that the SRAM cell layout is less in the first (word line) direction than in the second (bit line) direction as in the instant application).
Regarding independent claim 27, Fujiwara discloses a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell (Fig. 7 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a front-side contact over a frontside of a source/drain region of a first transistor of the first SRAM cell and a frontside of a source/drain region of a first transistor of the second SRAM cell (Fig. 7 where it illustrates the layout for s/d contact 402);
forming a front-side interconnection structure comprising a first bit line electrically coupled to the front-side contact (Fig. 7 where contact 402 is connected to the bit line BL. See also para. 38; "The S/D contact 402 is connected to the bit line BL");
Fujiwara is silent with respect to the bit line being on the back side.
However, Wang teaches forming a first back-side contact over a backside of a source/drain region of a second transistor of the first SRAM cell and a backside of a source/drain region of a second transistor of the second SRAM cell (Fig. 4C where it illustrates back side contact 302 connected to a drain 320. Additionally, Chen specifically teaches the technology and methodology used for GAA SRAM backside signal routing and the benefits thereof)
and forming a back-side interconnection structure comprising a second bit line electrically coupled to the first back-side contact (Fig. 4C where it illustrates back side contact 302 connected to a second bit line 456).
Fujiwara and Wang as supported by Chen are from the same field of endeavor as applicant’s invention directed to memory device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside power and bit lines on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 28, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 27.
As applied, Fujiwara further discloses wherein the first transistors of the first and second SRAM cells are first pass-gate transistors (Fig. 2: PG0)
and the second transistors of the first and second SRAM cells are second pass-gate transistors (Fig. 2: PG1)
Regarding claim 29, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 27.
As applied, Wang further discloses wherein the first bit line vertically overlaps the second bit line (Fig. 4C where it illustrates a first bit line 460 vertically above the second bit line 456. It is noted that the split bit line configuration - specifically partitioning one to the frontside and one to the backside - is well understood in the art as a cornerstone of backside power delivery network (BSPDN) integration with backside signals as supported by Chen. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the bit lines of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Chen (col. 1, sect. I - Introduction and Fig. 1 for example).The resulting physical layout directly below the frontside bit line is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting standard cell height requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods).
Claims 19, 31, 33-34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara”), in view of Wang (US 20190386062) as supported by Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen”) and further in view of Farooq et al. (US 20230230901; “Farooq”).
Regarding claim 19, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 17.
While Fujiwara and Wang combined disclose SRAM cells with a backside bit line, they are silent with regard to forming explicit backside interconnect structure.
However, Farooq teaches further comprising:
prior to forming the back-side interconnection structure, forming a backside contact over source/drain structures of second pass-gate transistors of the first and second SRAM cells.(Fig.1 where it illustrates the backside contacts to the drain/source of transistors 68, and the backside power distribution network 80. It is well understood in the art that, similar to the front side interconnection method, the backside process necessarily applies the contact layer before the interconnect layers. Additionally, Chen teaches routing of certain backside signals similarly to the power network).
Fujiwara and Wang as supported by Chen combined with Farooq are from the same field of endeavor as applicant’s invention directed to GAA device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Farooq’s backside power distribution contact structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 31, Fujiwara combined with Wang as supported by Chen disclose the limitations of claim 27.
Fujiwara and Wang are silent with respect to explicit backside power connected to active transistor area.
However, Farooq teaches wherein the back-side interconnection structure further comprises: forming a first power rail electrically coupled to a source/drain region of a third transistor of the first SRAM cell; and forming a second power rail electrically coupled to a source/drain region of a third transistor of the second SRAM cell (Fig. 1 where it illustrates a backside power rail 78 connecting to the S/D of a transistor 68. See also para. 23; " Described herein is a TSV and backside power distribution structure". It is noted that a plurality of Farooq's power rails can be similarly structured and deliver power to a plurality of transistors).
Fujiwara and Wang as supported by Chen combined with Farooq are from the same field of endeavor as applicant’s invention directed to GAA device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Farooq’s backside power distribution contact structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 33, Fujiwara and Wang as supported by Chen combined with Farooq disclose the limitations of claim 31.
As applied, Farooq further discloses wherein the second bit line, the first power rail, and the second power rail are of a same metallization layer of the back-side interconnection structure (Fig. 1 where it illustrates a backside power rail 78 connecting to the S/D of a transistor 68. See also para. 23; " Described herein is a TSV and backside power distribution structure". It is noted that it is well understood in the art that since the bit lines and power lines extend in the same direction, only one metallization layer would be required. Further, the technique of both power and signals routed on the backside is supported by the teachings of Chen).
Regarding claim 34, Fujiwara and Wang as supported by Chen combined with Farooq disclose the limitations of claim 31.
As applied, Wang as supported by Chen further disclose wherein the second bit line is between the first power rail and the second power rail in a top view (Fig. 4C where it illustrates a first bit line 460 vertically above the second bit line 456. It is noted that the split bit line configuration - specifically partitioning one to the frontside and one to the backside - is well understood in the art as a cornerstone of backside power delivery network (BSPDN) integration with backside signals as supported by Chen. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the bit lines of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Chen (col. 1, sect. I - Introduction and Fig. 1 for example).The resulting physical layout of the bitline between the power rails is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting backside minimum distance requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods.)
Regarding claim 36, Fujiwara and Wang as supported by Chen disclose the limitations of claim 27.
Fujiwara and Wang are silent with respect to an explicit isolation structure.
However, Farooq teaches further comprising:
forming an isolation structure in contact with and aligned with a gate structure of the first transistor of the first SRAM cell in a top view (Fig. 1 where it illustrates a forming an isolation structure (STI 70) aligned with a gate structure).
Fujiwara and Wang as supported by Chen combined with Farooq are from the same field of endeavor as applicant’s invention directed to GAA device layouts using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Farooq’s isolation structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller and faster due to reduced capacitive loading.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara”), in view of Wang (US 20190386062) as supported by Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen”) and further in view of Yeh et al. (US 20220020700; “Yeh”).
Regarding claim 30, Fujiwara and Wang as supported by Chen disclose the limitations of claim 27.
Fujiwara and Wang are silent with respect to the explicit layout geometries of the backside bitline.
However, Yeh teaches wherein the second bit line has a first line portion and a second line portion wider than the first line portion (Fig. 16 which illustrates a signal line with a first portion W3 and a second portion W2 wider than the first line portion. It is noted that this limitation appears to be directed to Fig. 13 of the instant application. It is well understood in the art that design requirements for backside routing (as supported by Chen) are similar to RDL (as in Yeh's top of chip redistribution layer) routing. Specifically, that the via structures are large relative to the structures they connect to and precise alignment to those structures is a fabrication challenge. The industry standard solution has long been to implement larger "endcaps" on routing lines (commonly referred to as a "dog bone" shape),
and the second line portion of the second bit line vertically overlaps the first back-side contact (The backside bit line must necessarily overlap the contact).
Fujiwara and Wang as supported by Chen combined with Yeh are from the same field of endeavor as applicant’s invention directed to integrated circuit device layouts using distribution layer interconnect techniques. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Yeh’s dog bone shape routing. Doing so would compact the layout of the memory cell improving device density and making the array smaller and faster due to reduced capacitive loading on the bitline.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara”), in view of Wang (US 20190386062) as supported by Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen”) and further in view of Yuh et al. (US 20230067715; “Yuh”)
Regarding claim 35, Fujiwara and Wang as supported by Chen disclose the limitations of claim 27.
Fujiwara and Wang are silent with respect to the explicit layout geometries of dummy transistors.
However, Yuh teaches further comprising:
forming a dummy transistor, wherein a gate structure of the dummy transistor is aligned with a gate structure of the first transistor of the first SRAM cell in a top view (Fig 5A: 150. See also para. 53; "the gate structures 150 are dummy (sacrificial) gate structures". It is noted that the GAA process which forms the structure of Yuh's device is identical to that of the instant application and thus, the placement of the dummy gate structures would simply be a design choice serving the same purpose)
Fujiwara and Wang as supported by Chen combined with Yuh are from the same field of endeavor as applicant’s invention directed to memory devices using backside interconnect. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Yuh’s dummy transistors. Doing so would compact the layout of the memory cell improving device density and making the array smaller and more uniform due to improved planarity.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara”), in view of Wang (US 20190386062) as supported by Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen”) and further in view of Farooq et al. (US 20230230901; “Farooq”) and further in view of Yeh et al. (US 20220020700; “Yeh”).
Regarding claim 32, Fujiwara and Wang as supported by Chen combined with Farooq disclose the limitations of claim 31.
Fujiwara and Wang combined with Farooq are silent with respect to the explicit layout geometries of the backside bitline.
However, Yeh teaches further comprising:
forming a second back-side contact over a backside of the source/drain region of the third transistor of the first SRAM cell, wherein the first power rail is coupled to the second back-side contact, and the first power rail has a main line and an extending portion on a side of the main line, and the extending portion of the first power rail vertically overlaps the second back-side contact (Fig. 16 which illustrates a line with a first portion W3 and a second portion W2. It is noted that this limitation appears to be directed to Fig. 12 of the instant application and specifically where the line has a bump out to accommodate the backside contact and therefore demonstrates using a different width of a routing layer to achieve a design rule. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the backside power line feeding the transistors of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Farooq and supported Chen. The resulting physical bump out layout directly adjacent to the transistor source terminal is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting backside contacting requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods).
Fujiwara and Wang as supported by Chen combined with Yeh are from the same field of endeavor as applicant’s invention directed to integrated circuit device layouts using distribution layer interconnect techniques. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s GAA SRAM cell pair with Wang’s backside bit lines and with Yeh’s bump out shape for routing the bitline. Doing so would compact the layout of the memory cell improving device density and making the array smaller and improving manufacturability by improving contact alignment margins.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825