DETAILED ACTION
This action is responsive to the amendments filed May 5, 2025. Claims 17-36 are pending. Claims 17, 21, and 27 have been amended. Claims 17, 21, and 27 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant's amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Applicants amendments to the specification to para. 24, 64, and 66 addressing figure labeling consistency and correcting minor typographical errors is acknowledged and accepted. The further objection to the specification has been withdrawn.
Election/Restrictions
Claims 21-36 remain under examination. Although upon reconsideration, these claims are merely product-by-process re-writes of the non-elected Group I, and correspond expressly to the subject matter originally presented as claims 1-16, they were examined on the merits in the previous Office action. The restriction is therefore considered waived as to claims 21-36, and these claims are treated as elected for the purposes of the present examination.
The election of Group II remains in effect for any other purposes.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 17-18, 20-29, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara” – of record), in view of Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen” – of record) as supported by Yuh et al. (US 20230067715; “Yuh” – of record)
Regarding independent claim 17, Fujiwara discloses a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell over a substrate, wherein the first and second SRAM cells are arranged along a first direction in a top view (Figs. 7-9 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a front-side interconnection structure over a frontside of the substrate, wherein the front-side interconnection structure comprises:
a first word line and a second word line extending along the first direction and respectively coupled to the first and second SRAM cell (Fig. 7 where it illustrates the layout for a first and second word line WL0 and WL1 in a first direction (Y) and coupled to the first and second SRAM cell respectively);
and a first bit line extending along a second direction different from the first direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the layout for the bit line BL extending in a second direction and coupled to the first and second SRAM cells. See also para. 61; "the shared S/D contact 402 … is connected to the bit line BL");
wherein the first bit line in the front-side interconnection structure and the second bit line ( … ) constitute a complementary bit line pair for the first and second SRAM cells (Abstr. "the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell.").
wherein the ( … ) interconnection structure comprises a second bit line extending along the second direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates both bit line BL and bit line bar BLB extending in a second direction (X in this case) and coupled to the first and second SRAM cell respectively),
While Fujiwara discloses adjacent SRAM cells with a shared front-side bit line and a complementary bit line pair coupled to both cells via shared source/drain contacts and extending in the same (second) direction, it is silent with respect to the second bit line as explicitly being part of a back-side interconnect structure.
However, Chen teaches and forming a back-side interconnection structure over a backside of the substrate (as well as) in the back-side interconnection structure ((Abstr.; "backside (BS) interconnect for signal routing in SRAM macro", see also sect. II.C; " BS routing starts from the FS M1 pins and then goes through the nTSV to the BS metals". It is noted that the recited advantages of Chen's back-side interconnect specifically for signal routing in SRAM macros, namely alleviating front-side routing congestion and improving performance of the SRAM array are analogous to those suggested by the instant application for the same structures. Regarding the back-side interconnect being explicitly labeled a "bit line", Yuh further supports distributing bit lines across front-side and back-side interconnect structures in memory arrays (see for example Fig. 33)).
Fujiwara and Chen as supported by Yuh are from the same field of endeavor as applicant’s invention directed to design and layout methods of advanced-node SRAM cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SRAM cell pair and complimentary bit line pair of Fujiwara by placing one line of the complimentary pair on the backside using the backside interconnect techniques taught by Chen (as supported by Yuh). Doing so would alleviate frontside BEOL congestion, reduce MEOL and BEOL capacitance and resistance thereby improving performance and enabling further cell scaling. The combination yields the predictable results using known methods and techniques.
Regarding claim 18, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 17.
As applied, Fujiwara further discloses further comprising:
prior to forming the front-side interconnection structure, forming a frontside contact over source/drain structures of first pass-gate transistors of the first and second SRAM cells (Fig. 6 where it illustrates source and drain contacts. It is well understood in the art that the contact layer is necessarily formed before the upper interconnect layers).
Regarding claims 20, 22 and 29, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claims 17, 21 and claim 27 respectively.
Claims 20, 22 and 29 further recite: wherein the first bit line vertically overlaps the second bit line.
Fujiwara discloses a complementary bit line pair (BL and BLB) coupled to the first and second SRAM cells and extends in the second direction (see Fig. 7 for example). Fujiwara is silent with respect to the first and second bit line vertically overlapping because both bit lines of the complementary pair are formed on the frontside.
Chen teaches the use of backside interconnects for signal routing, including bit lines, in SRAM macros (see Abstr. as well as sect. II.C).
As further supported by Yuh (see simplified cross-sectional view in Fig. 33), the frontside bit line (BL1) and the backside bit lines (BL2), are positioned in corresponding locations relative to the underlying memory cells and run in the same direction, resulting in vertical overlap.
The vertical overlap is an inherent geometric result of the combination and is not patentably distinct. There is no unexpected results associated with the overlap itself. It is merely the natural consequence of stacking the complimentary lines on opposite sides of the device layer in corresponding positions for the same SRAM cells.
Regarding independent claim 21, Fujiwara discloses a method, comprising:
forming a device layer comprising a first static random access memory (SRAM) cell and a second SRAM cell arranged along a first direction in a top view (Fig. 7-9 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a first word line extending along the first direction and electrically coupled to the first SRAM cell (Fig. 7 where it illustrates the layout for a first word line WL0 in a first direction (Y) and coupled to the first SRAM cell respectively);
forming a second word line extending along the first direction and electrically coupled to the second SRAM cell (Fig. 7 where it illustrates the layout for second word line WL1 in a first direction (Y) and coupled to the second SRAM cell respectively);
forming a first bit line over a frontside of the device layer, wherein the first bit line extends along a second direction and electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the layout for the bit line BL extending in a second direction and coupled to the first and second SRAM cells. See also para. 61; "the shared S/D contact 402 … is connected to the bit line BL");
and the second direction is different from the first direction in the top view (Fig. 7 where it illustrates the first direction in Y and the second direction in X);
( … ) wherein the second bit line extends along the second direction and is electrically coupled to the first and second SRAM cells (Fig. 7 where it illustrates the second bit line BLB extending in the second direction and coupled the first and second SRAM cells).
While Fujiwara discloses adjacent SRAM cells with a shared front-side bit line and a complementary bit line pair coupled to both cells via shared source/drain contacts and extending in the same (second) direction, it is silent with respect to the second bit line as explicitly being part of a back-side interconnect structure.
However, Chen teaches and forming a second bit line over a backside of the device layer ( … ) wherein the first bit line over the frontside of the device layer and the second bit line over the backside of the device layer constitute a complementary bit line pair for the first and second SRAM cells (Abstr.; "backside (BS) interconnect for signal routing in SRAM macro", see also sect. II.C; " BS routing starts from the FS M1 pins and then goes through the nTSV to the BS metals". It is noted that the recited advantages of Chen's back-side interconnect specifically for signal routing in SRAM macros, namely alleviating front-side routing congestion and improving performance of the SRAM array are analogous to those suggested by the instant application for the same structures. Regarding the back-side interconnect being explicitly labeled a "bit line", Yuh further supports distributing bit lines across front-side and back-side interconnect structures in memory arrays (see for example Fig. 33)).
Fujiwara and Chen as supported by Yuh are from the same field of endeavor as applicant’s invention directed to design and layout methods of advanced-node SRAM cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SRAM cell pair and complimentary bit line pair of Fujiwara by placing one line of the complimentary pair on the backside using the backside interconnect techniques taught by Chen (as supported by Yuh). Doing so would alleviate frontside BEOL congestion, reduce MEOL and BEOL capacitance and resistance thereby improving performance and enabling further cell scaling. The combination yields the predictable results using known methods and techniques.
Regarding claim 23, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 21.
As applied, Fujiwara further discloses wherein the first and second word lines are over the frontside of the device layer (Fig. 7 where it illustrates a first word line WL0 and a second word line WL1 as an M2 line over the frontside).
Regarding claim 24, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 21.
As applied, Fujiwara further discloses further comprising:
forming a third word line extending along the first direction; and forming a fourth word line extending along the first direction (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where word line WL[2] and WL[3] would be the third and fourth word lines for example),
wherein the device layer further comprises a third SRAM cell and a fourth SRAM cell (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where the pair of cells 410 and 450 in position 3B would be the third and fourth SRAM cells for example),
the third and fourth SRAM cells are respectively electrically coupled to the third and fourth word lines (Fig. 9 (see configuration description above)).
and each of the third and fourth SRAMs cells is electrically coupled to the first bit line and the second bit line (Fig. 9 where BL[2] and BLB[2] are the first and second bit lines for example).
Regarding claim 25, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 21.
As applied, Fujiwara further discloses further comprising:
forming a third bit line extending along the second direction; and forming a fourth bit line extending along the second direction (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where bit lines BL[1] and BLB[1] would be the third and fourth bit lines for example),
wherein the device layer further comprises a fifth SRAM cell and a sixth SRAM cell, (Fig. 9 where it illustrates an array of SRAM cells in a 3x3 grid, where the pair cells 401 and 450 in position 2A would be the fifth and sixth SRAM cells for example),
the fifth and sixth SRAM cells are respectively electrically coupled to the first and second word lines (Fig. 9 where WL[5] and WL[4] are the first and second word lines for example),
and each of the fifth and sixth SRAM cells is electrically coupled to the third bit line and the fourth bit line (Fig. 9 (see configuration description above)).
Regarding claim 26, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 21.
As applied, Fujiwara further discloses wherein a length of the first SRAM cell measured along the first direction is less than a length of the first SRAM cell measured along the second direction in the top view (Fig. 7 where it illustrates that the SRAM cell layout is less in the first (word line) direction than in the second (bit line) direction as in the instant application).
Regarding independent claim 27, Fujiwara discloses a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell (Figs. 7-9 where it illustrates the layout for a first and second static random access memory cell 410 and 450 in a first direction (Y in this case));
forming a front-side contact over a frontside of a source/drain region of a first transistor of the first SRAM cell and a frontside of a source/drain region of a first transistor of the second SRAM cell (Fig. 7 where it illustrates the layout for s/d contact 402);
forming a front-side interconnection structure comprising a first bit line electrically coupled to the front-side contact (Fig. 7 where contact 402 is connected to the bit line BL. See also para. 38; "The S/D contact 402 is connected to the bit line BL");
wherein the first bit line in the front-side interconnection structure and the second bit line ( … ) constitute a complementary bit line pair for the first and second SRAM cells (Abstr. "the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell.").
While Fujiwara discloses adjacent SRAM cells with a shared front-side bit line and a complementary bit line pair coupled to both cells via shared source/drain contacts and extending in the same (second) direction, it is silent with respect to the second bit line as explicitly being part of a back-side interconnect structure
However, Chen (as supported by Yuh) teaches in the back-side interconnection structure (as well as) forming a first back-side contact over a backside of a source/drain region of a second transistor of the first SRAM cell and a backside of a source/drain region of a second transistor of the second SRAM cell; and forming a back-side interconnection structure comprising a second bit line electrically coupled to the first back-side contact (Abstr.; "backside (BS) interconnect for signal routing in SRAM macro", see also sect. II.C; " BS routing starts from the FS M1 pins and then goes through the nTSV (back-side contact) to the BS metals". It is noted that the recited advantages of Chen's back-side interconnect specifically for signal routing in SRAM macros, namely alleviating front-side routing congestion and improving performance of the SRAM array are analogous to those suggested by the instant application for the same structures. Regarding back-side contacts over the source/drain of the transistors Yuh supports explicitly supports this requirement (see Abstr.; "contact feature is connected with a back side of a first source/drain feature of the transistor device), and regarding the interconnect being explicitly labeled a "bit line", Yuh further supports distributing bit lines across front-side and back-side interconnect structures in memory arrays (see for example Fig. 33 where it illustrates BL2)).
Fujiwara and Chen as supported by Yuh are from the same field of endeavor as applicant’s invention directed to design and layout methods of advanced-node SRAM cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SRAM cell pair and complimentary bit line pair of Fujiwara by placing one of the shared contacts and one line of the complimentary pair on the backside using the backside interconnect techniques taught by Chen (as supported by Yuh). Doing so would alleviate frontside BEOL congestion, reduce MEOL and BEOL capacitance and resistance thereby improving performance and enabling further cell scaling. The combination yields the predictable results using known methods and techniques.
Regarding claim 28, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 27.
As applied, Fujiwara further discloses wherein the first transistors of the first and second SRAM cells are first pass-gate transistors (Fig. 2: PG0)
and the second transistors of the first and second SRAM cells are second pass-gate transistors (Fig. 2: PG1)
Regarding claim 35, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 27.
As applied, Yuh (as support for Chen) specifically teaches further comprising:
forming a dummy transistor, wherein a gate structure of the dummy transistor is aligned with a gate structure of the first transistor of the first SRAM cell in a top view (Fig 5A: 150. See also para. 53; "the gate structures 150 are dummy (sacrificial) gate structures". It is noted that the GAA process which forms the structure of Yuh's device is identical to that of the instant application and thus, the placement of the dummy gate structures would simply be a design choice serving the same purpose)
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara” – of record), in view of Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen” – of record) as supported by Yuh et al. (US 20230067715; “Yuh” – of record), and further in view of Yeh et al. (US 20220020700; “Yeh”).
Regarding claim 30, Fujiwara and Chen as supported by Yuh disclose the limitations of claim 27.
Fujiwara and Chen as supported by Yuh are silent with respect to the explicit layout geometries of the backside bitline.
However, Yeh teaches wherein the second bit line has a first line portion and a second line portion wider than the first line portion (Fig. 16 which illustrates a signal line with a first portion W3 and a second portion W2 wider than the first line portion. It is noted that this limitation appears to be directed to Fig. 13 of the instant application. It is well understood in the art that design requirements for backside routing (as supported by Chen) are similar to RDL (as in Yeh's top of chip redistribution layer) routing. Specifically, that the via structures are large relative to the structures they connect to and precise alignment to those structures is a fabrication challenge. The industry standard solution has long been to implement larger "endcaps" on routing lines (commonly referred to as a "dog bone" shape),
and the second line portion of the second bit line vertically overlaps the first back-side contact (The backside bit line must necessarily overlap the contact).
Fujiwara and Chen as supported by Yuh combined with Yeh are from the same field of endeavor as applicant’s invention directed to integrated circuit device layouts using distribution layer interconnect techniques. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s SRAM cell pair with Chen’s (as supported by Yuh) backside bit lines and with Yeh’s dog bone shape routing. Doing so would compact the layout of the memory cell improving device density and making the array smaller and faster due to reduced capacitive loading on the bitline.
Claims 19, 31, 33-34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara” – of record), in view Chen et al, (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen” – of record) supported by Yuh et al. (US 20230067715; “Yuh” – of record), and further in view of Farooq et al. (US 20230230901; “Farooq” – of record).
Regarding claim 19, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 17.
While Fujiwara and Chen as supported by Yuh combined disclose SRAM cells with a backside bit line, they are silent with regard to forming explicit backside interconnect structure.
However, Farooq teaches further comprising:
prior to forming the back-side interconnection structure, forming a backside contact over source/drain structures of second pass-gate transistors of the first and second SRAM cells.(Fig.1 where it illustrates the backside contacts to the drain/source of transistors 68, and the backside power distribution network 80. It is well understood in the art that, similar to the front side interconnection method, the backside process necessarily applies the contact layer before the interconnect layers. Additionally, Chen teaches routing of certain backside signals similarly to the power network).
Fujiwara and Chen as supported by Yuh combined with Farooq are from the same field of endeavor as applicant’s invention directed to advanced-node SRAM device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s SRAM cell pair with Chen’s (as supported by Yuh) backside bit lines and with Farooq’s backside power distribution contact structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 31, Fujiwara combined with Chen as supported by Yuh disclose the limitations of claim 27.
Fujiwara and Chen as supported by Yuh are silent with respect to explicit backside power connected to active transistor area.
However, Farooq teaches wherein the back-side interconnection structure further comprises: forming a first power rail electrically coupled to a source/drain region of a third transistor of the first SRAM cell; and forming a second power rail electrically coupled to a source/drain region of a third transistor of the second SRAM cell (Fig. 1 where it illustrates a backside power rail 78 connecting to the S/D of a transistor 68. See also para. 23; " Described herein is a TSV and backside power distribution structure". It is noted that a plurality of Farooq's power rails can be similarly structured and deliver power to a plurality of transistors).
Fujiwara and Chen as supported by Yuh combined with Farooq are from the same field of endeavor as applicant’s invention directed to advanced-node SRAM device layouts. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s SRAM cell pair with Chen’s (as supported by Yuh) backside bit lines and with Farooq’s backside power distribution contact structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller.
Regarding claim 33, Fujiwara and Chen as supported by Yuh combined with Farooq disclose the limitations of claim 31.
As applied, Farooq further discloses wherein the second bit line, the first power rail, and the second power rail are of a same metallization layer of the back-side interconnection structure (Fig. 1 where it illustrates a backside power rail 78 connecting to the S/D of a transistor 68. See also para. 23; " Described herein is a TSV and backside power distribution structure". It is noted that it is well understood in the art that since the bit lines and power lines extend in the same direction, only one metallization layer would be required. Further, the technique of both power and signals routed on the backside is supported by the teachings of Chen).
Regarding claim 34, Fujiwara, Chen as supported by Yuh, and Farooq combine to disclose the limitations of claim 31.
As applied, Fujiwara further discloses wherein the second bit line is between the first power rail and the second power rail in a top view (Fig. 7 a top view illustrating both bit lines (BL and BLB) between power rail VDD and VSS).
Fujiwara in view of Chen as supported by Yuh (as applied to claim 31) disclose the complimentary bit line pair with one line and the power rails on the backside, but is less explicit with respect to the precise top-view ordering in which the second bit line is located between the first power rail and the second power rail.
Farooq teaches a backside power distribution structure that includes backside power rails positioned closest to the devices for efficient power delivery and reduced IR droop.
The arrangement of the backside bit line between the first and second backside power rails in a top-view is nothing more than the conventional relative ordering already taught by Fujiwara for the frontside equivalent lines. The resulting physical layout is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting backside minimum distance requirements) on the backside (using the techniques of Chen/Yuh/Farooq). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods.)
Regarding claim 36, Fujiwara and Chen as supported by Yuh disclose the limitations of claim 27.
Fujiwara and Chen as supported by Yuh are silent with respect to an explicit isolation structure.
However, Farooq teaches further comprising:
forming an isolation structure in contact with and aligned with a gate structure of the first transistor of the first SRAM cell in a top view (Fig. 1 where it illustrates a forming an isolation structure (STI 70) aligned with a gate structure).
Fujiwara and Chen as supported by Yuh combined with Farooq are from the same field of endeavor as applicant’s invention directed to advanced-node SRAM device layouts. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s SRAM cell pair with Chen’s (as supported by Yuh) backside bit lines and with Farooq’s isolation structure on the same device. Doing so would compact the layout of the memory cell improving device density and making the array smaller and faster due to reduced capacitive loading.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al. (US 20210366915; “Fujiwara” – of record), in view of Chen et al (“Design and Optimization of SRAM Macro and Logic Using Backside Interconnects”; “Chen” – of record) as supported by Yuh et al. (US 20230067715; “Yuh” – of record), and further in view of Farooq et al. (US 20230230901; “Farooq” – of record), and further in view of Yeh et al. (US 20220020700; “Yeh” – of record).
Regarding claim 32, Fujiwara, Chen as supported by Yuh, and Farooq combined disclose the limitations of claim 31.
Fujiwara, Chen as supported by Yuh, and Farooq combined are silent with respect to the explicit layout geometries of the backside bitline.
However, Yeh teaches further comprising:
forming a second back-side contact over a backside of the source/drain region of the third transistor of the first SRAM cell, wherein the first power rail is coupled to the second back-side contact, and the first power rail has a main line and an extending portion on a side of the main line, and the extending portion of the first power rail vertically overlaps the second back-side contact (Fig. 16 which illustrates a line with a first portion W3 and a second portion W2. It is noted that this limitation appears to be directed to Fig. 12 of the instant application and specifically where the line has a bump out to accommodate the backside contact and therefore demonstrates using a different width of a routing layer to achieve a design rule. A person of ordinary skill in the art of integrated circuit layout design would have found it obvious to arrange the backside power line feeding the transistors of the well-known 6T SRAM schematic of the instant application, using the design practices taught by Farooq and supported Chen. The resulting physical bump out layout directly adjacent to the transistor source terminal is merely a predictable outcome of applying routine engineering skills and known design constraints (such as minimizing area, optimizing routing for speed, and meeting backside contacting requirements). There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods).
Fujiwara, Chen as supported by Yuh, and Farooq combined, along with Yeh are from the same field of endeavor as applicant’s invention directed to integrated circuit device layouts using distribution layer interconnect techniques. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fujiwara’s SRAM cell pair with Chen’s (as supported by Yuh) backside bit lines and with Yeh’s bump out shape for routing the bitline. Doing so would compact the layout of the memory cell improving device density and making the array smaller and improving manufacturability by improving contact alignment margins.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant contends on pg. 11 of Remarks that the obviousness rejection for independent claim 17 is improper. Applicant has amended independent claim 17 to recite, inter alia, that “the first bit line in the front-side interconnection structure and the second bit line in the back-side interconnection structure constitute a complementary bit line pair for the first and second SRAM cells.” To support their argument, Applicant asserts the rejection was on the ground that Wang’s front-side and back-side bit lines are associated with different, independent memory devices (e.g., MRAM on one side and RRAM on the other) rather than forming a complementary pair for the same SRAM cells. Applicant further contends that Chen does not cure this alleged deficiency.
The present Office action obviousness rejection above is based on Fujiwara as the primary reference in view of Chen as supported by Yuh. Fujiwara discloses a method of forming adjacent SRAM cells (410 and 450) arranged along a first direction, with respective word lines (WL0 and WL1) coupled to each cell, and a shared front-side bit line (BL) coupled to both cells via a shared source/drain contact. Fujiwara further discloses that the cells share a complementary bit line pair, with the shared contacts connecting to both the bit line and the complementary bit line bar for the same cells.
Fujiwara discloses the SRAM cell pair, the respective word lines, the shared front-side bit line, and a true complementary bit line pair serving those cells but is silent with respect to placing one line of that complementary pair in a back-side interconnection structure. Chen teaches backside interconnects specifically for signal routing in SRAM macros, including backside metals connected through nTSVs, and explicitly demonstrates performance and power efficiency improvements from moving SRAM signal routing (including bit lines) to the backside. Yuh further teaches the distribution of bit lines across front-side and back-side interconnect structures in memory arrays, including configurations in which even-numbered and odd-numbered memory structures are connected to bit lines on opposite sides to achieve wider lines, reduced resistance, denser arrays, and reduced coupling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujiwara’s SRAM cell pair having a complementary bit line pair by placing one of the lines of that pair on the backside using the known backside interconnect technique taught by Chen and Yuh. The resulting structure has a front-side first bit line and a back-side second bit line that together constitute a complementary bit line pair for the first and second SRAM cells, exactly as recited in amended claim 17. The motivation to combine is explicit in Chen (quantified SRAM macro performance and power gains from backside routing) and Yuh (density and RC benefits from front/back bit line distribution in memory arrays). The combination is nothing more than the predictable use of a known backside routing technique in the specific context of Fujiwara’s already-disclosed SRAM complementary pair.
Applicant’s argument directed to Wang’s use of different memory device types are moot because Wang is no longer relied upon in the present rejection. Additionally, the functional label "complementary bit line pair" does not patentably distinguish the claim when both the pair (Fujiwara) and the backside placement technique (Chen as supported by Yuh) are taught in the prior art.
The same reasoning applies to independent claims 21 and 27 which were amended similarly. All other claims depend from claims 17, 21, and 27 and are therefore also rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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