Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/20/2026 under 37 CFR 1.131 has been considered.
Applicant’s arguments (incorporating previously indicated allowable subject matter) with respect to claims 1-6, 9-12, 21 are persuasive, accordingly, claims 1-6, 9-12, 21 are allowed.
Applicant’s arguments with respect to claims 13-16, 22 are moot in view of the rejection below.
Applicant’s arguments with respect to claims 17-20 are ineffective to overcome the cited reference as discussed below.
DETAILED ACTION
This action is responsive to application No. 18420550 filed on 01/23/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gandikota et al. (US 2024/0363723) in view of Lin et al. (US 2022/0344354).
Regarding Independent claim 13, Gandikota et al. teach method comprising:
forming an interfacial layer (Fig. 2B, element 210, paragraph 0088) on a first semiconductor region (Fig. 2B, left channel 206) and a second semiconductor region (Fig. 2B, right channel 206);
forming a first high-k dielectric layer (Fig. 2B, element 212, paragraph 0089) on the interfacial layer and on the first semiconductor region and the second semiconductor region;
depositing a dipole film (Fig. 2B, element 214, paragraph 0091) on the first high-k dielectric layer, wherein the dipole film comprises a first portion overlapping the first semiconductor region and a second portion overlapping the second semiconductor region (Fig. 2B);
performing a plasma treatment process (paragraph 0056-0062) on the dipole film;
removing the second portion of the dipole film (paragraph 0110-0112);
performing a drive-in process (Fig. 2E, element 160, paragraph 0075-0076) to drive a dipole dopant in the dipole film into the first high-k dielectric layer; and
forming a first gate electrode (Fig. 2F, element 218, paragraph 0119) and a second gate electrode (Fig. 2F, element 218, paragraph 0119) on the first high-k dielectric layer,
wherein the first gate electrode and the second gate electrode are on the first semiconductor region and the second semiconductor region, respectively (Fig. 2F).
Gandikota et al. do not explicitly disclose after the dipole film is deposited, performing a plasma treatment process on the dipole film.
Lin et al. teach a method comprising after the dipole film (Fig.s 16 & 15, elements 402/404/406, paragraph 0043) is deposited, performing a plasma treatment process on the dipole film (paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Gandikota et al. according to the teachings of Lin et al. with the motivation to remove the dipole layer (paragraph 0043).
Regarding claim 14, Gandikota et al. teach wherein the plasma treatment process is performed using a process gas comprising nitrogen and hydrogen (paragraph 0056-0062).
Regarding claim 15, Gandikota et al. teach wherein the first semiconductor region and the first semiconductor region are semiconductor nanostructures (paragraph 0039-0040), and wherein the first portion and the second portion of the dipole film encircle the first semiconductor region and the second semiconductor region, respectively (paragraph 0039-0040, in a gate-all-around channel nanostructure the dipole would encircle the channel regions).
Regarding claim 22, Gandikota et al. modified by Lin et al. teach wherein the dipole film is deposited using precursors, and the plasma treatment process is performed using process gases different from the precursors (paragraph 0056-0062 of Gandikota and paragraph 0043 of Lin).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gandikota et al. (US 2024/0363723) in view of Lin et al. (US 2022/0344354) and further in view of Lin et al. (US 2024/0387286).
Regarding claim 16, Gandikota et al. teach depositing a second high-k dielectric (Fig. 2F, element 216A, paragraph 0120) layer on the first high-k dielectric layer.
Gandikota et al. modified by Lin et al. do not explicitly disclose removing the dipole film after the drive-in process.
Lin et al. (286) teach a method comprising removing (Figs. 1A & 2U, paragraph 0122) the dipole film (Figs. 1A & 2C, element 274, paragraph 0086) after the drive-in process (Figs. 1A & 2T, element 302, paragraph 0119).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Gandikota et al. and Lin et al. according to the teachings of Lin et al. (286) with the motivation to manufacture CFETs that meet reduced thickness, reduced leakage, lower thermal budget, and V.sub.t requirements (paragraph 0014).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2024/0387286).
Regarding Independent claim 17, Lin et al. teach method comprising:
depositing a high-k dielectric layer (Figs. 1A & 2B, element 272, paragraph 0084) encircling a semiconductor nanostructure (Figs. 1B & 2A, element 230, paragraph 0068);
depositing a dipole film (Figs. 1A & 2C, element 274, paragraph 0086) encircling the high-k dielectric layer;
trimming the dipole film (paragraph 0094-0097), wherein an upper portion of the dipole film is removed, and a lower portion of the dipole film covered by the upper portion remains after the dipole film is trimmed (paragraph 0097 discloses “It has been found that selectively etching the vertically stacked superlattice structure 260 at operation 20 to remove the first protective layer 278 from the first portion 202-1 of the semiconductor substrate, and a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 from the second portion 202-2 of the semiconductor substrate, and increasing a thickness of the dipole layer (e.g., by depositing a second p-type dipole layer 280 at operation 24) advantageously provides a CFET 200 with multi-V.sub.t”);
performing a treatment process on the dipole film using nitrogen (N.sub.2) and hydrogen (H.sub.2) (paragraph 0087-0090);
performing an anneal process (Figs. 1A & 2T, element 302, paragraph 0119) on the dipole film that has been treated;
removing the dipole film (Figs. 1A & 2U, paragraph 0122);
depositing a second high-k dielectric layer (Figs. 1A & 2G, element 280, paragraph 0098) on the high-k dielectric layer; and
forming a gate electrode on the second high-k dielectric layer (paragraph 0123-0126).
Regarding claim 18, Lin et al. teach wherein the treatment process is performed through plasma treatment process (paragraph 0087-0090).
Regarding claim 19, Lin et al. teach wherein the depositing the dipole film comprises depositing aluminum oxide (paragraph 0086).
Regarding claim 20, Lin et al. teach wherein the depositing the dipole film comprises depositing lanthanum oxide (paragraph 0105).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813
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