Prosecution Insights
Last updated: October 01, 2026
Application No. 18/420,674

PHOTONIC DEVICE AND FABRICATING METHOD THEREOF

Non-Final OA §102
Filed
Jan 23, 2024
Examiner
LEE, CHEUNG
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1074 granted / 1165 resolved
+24.2% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
17 currently pending
Career history
1168
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
42.5%
+2.5% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
13.2%
-26.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1165 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Invention I, claims 1-11, in the reply filed on May 19, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). The newly added claims 21-29 are fully examined for patentability. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “PHOTONIC DEVICE HAVING A WAVEGUIDE STRUCTURE AND FABRICATING METHOD THEREOF.” If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 9 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ryan et al. (US Pub. 2025/0231342; hereinafter “Ryan”). Regarding Claim 9, Ryan discloses a method for fabricating a photonic device, comprising: providing an oxide layer 312 (BOX; page 5, paragraph 52) and a semiconductor layer (epitaxially grown silicon layer of an SOI wafer; page 5, paragraph 52) on the oxide layer 312 (see fig. 3A); forming a first waveguide structure 202 (page 3, paragraph 30) on the oxide layer 312 (the first waveguide 202 is formed on a bottom side of the oxide layer 312; see fig. 4A); and forming an electro-optical device 304 (page 5, paragraph 52) on a side (top side) of the oxide layer 312 opposite to the first waveguide structure 202 (see fig. 4A), wherein forming the electro-optical device 304 comprises patterning the semiconductor layer (the epitaxially grown silicon layer of the SOI wafer) to form a semiconductor structure of the electro-optical device 304 (the epitaxially grown silicon layer of the SOI wafer has been patterned to form a p-n junction phase modulator 304; page 5, paragraph 52). Allowable Subject Matter Claims 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 10 recites the semiconductor structure of the electro-optical device is optically coupled to the first waveguide structure through the oxide layer. Claim 11 recites forming a second waveguide structure on the side of the oxide layer opposite to the first waveguide structure, wherein a refractive index of the second waveguide structure is higher than a refractive index of the first waveguide structure. These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record. Claims 1-8 and 21-29 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 1 recites forming a first active device above a second side of the buried oxide layer opposite to the first side, wherein the first active device is optically coupled to the first waveguide structure. Claim 21 recites forming a semiconductor-insulator-capacitor modulator formed on the second surface of the oxide layer, wherein the semiconductor-insulator-capacitor modulator comprises: a first terminal optically connected with the first waveguide structure; a second terminal; and a capacitor dielectric layer disposed between the first terminal and the second terminal. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record. Claims 2-8 and 22-29 variously depend from claim 1 or 21, so they are allowed for the same reason. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHEUNG LEE/Primary Examiner, Art Unit 2812 August 19, 2026
Read full office action

Prosecution Timeline

Jan 23, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740392
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 9m to grant Granted Sep 15, 2026
Patent 12740132
SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN CONTACT MOL CUT STRUCTURE
2y 6m to grant Granted Sep 15, 2026
Patent 12740065
NON-VOLATILE MEMORY
2y 5m to grant Granted Sep 15, 2026
Patent 12727516
INTEGRATED CIRCUITS WITH SELECTABLE PACKAGING TYPES
2y 6m to grant Granted Sep 01, 2026
Patent 12721010
METHOD OF MANUFACTURING DISPLAY DEVICE
2y 9m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
96%
With Interview (+4.3%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1165 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month