DETAILED ACTION
This action is responsive to the application No. 18/420,779 filed on January 24, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 10,515,853) in view of Wei (10,685,883), all of record.
(Re Claim 1) Chen teaches a method of dicing a wafer, comprising (see Figs. 1-2O and supporting text):
providing a wafer (W) with a front side (FS) and a back side (BS), wherein a first die (D on right side), a second die (D on left side), and a scribe line (SLR) are disposed on the front side of the wafer, the scribe line is positioned between the first die and the second die (Fig. 2A), a test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is disposed on the dielectric layer (see detail of test structure TE in SLS: 102, 104, 106, P), the first die (D) comprises a first dielectric layer and a first metal connection disposed within and on the first dielectric layer (not shown, discussed below), two first trenches are respectively disposed within the dielectric layer at two sides of the test structure and the wafer is exposed through the two first trenches (trenches formed in Fig. 2C);
providing a grinding tape (GTP) covering the front side of the wafer and contacting the test structure (S104, Fig. 2E); planarizing the back side of the wafer to thin the wafer (S106, Fig. 2F, col 5 lines 7-25); and
after thinning the wafer, performing a plasma process, wherein the plasma process comprises: etching the back side of the wafer to form two second trenches respectively penetrating the wafer, wherein each of the two second trenches respectively connects to a corresponding one of the two first trenches (S116, Figs. 2L-2M, col 6 lines 19-48).
Chen lacks details of the structures within the dies. A PHOSITA would recognize the dies will contain numerous layers/structures in order to function and would be motivated to look to related art to teach details of the dies where Chen is silent. Related art from Wei shows (Fig. 2A) how the dielectric layers 102 and metal connection structures (V1, V1’, V2, V2’, V3, V3’, M1, M1’, M2, M2’, etc.) extend from within the scribe line region into the dies as this is a conventional construction. Test structures in dicing lines are often formed simultaneously with the interconnect structures of the dies and share the same ILD and metal layers as shown by Wei. In view of Wei and Chen’s depiction of SLS, a PHOSITA would find it obvious that the dielectric and metal layers within Chen’s SLR region are similarly formed in the die regions according to Wei.
(Re Claim 2) wherein the second die (D) comprises a second metal connection and a second dielectric layer, the second metal connection is disposed within and on the second dielectric layer (all dies D of the wafer are understood to be the same, Chen Fig. 2M in view of Wei’s Fig. 2A teaching the dies comprise the same dielectric and metal layers as in the SLS).
(Re Claim 6) wherein an etchant gas used in the plasma process comprises SF6, CF4/O2, CF2Cl2, CF3Cl, SF6/O2/Cl2, Cl2/H2/C2F6/CCl4, C2ClF5/O2, SiF4/O2, NF3, ClF3, CCl4, CCl3F5, C2ClF5/SF6, C2F6/CF3Cl, Br2 or CF3Cl/Br2.
Chen is discloses etching using “sulfur fluoride” (col 6 line 45-48), understood to be the well-known and perhaps one of the most common plasma etchants used in semiconductor fabrication: sulfur hexafluoride (SF6). Related art from Wei teaches plasma etching using SF6 (col 6 lines 15-17). A PHOSITA would find SF6 obvious in light of Chen’s disclosure of sulfur fluoride and Wei’s disclosure of SF6 for the plasma etching.
(Re Claim 8) wherein during the plasma process, the test structure is not removed (Figs. 2C-2D).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. and Wei (10,685,883) as applied above, and further in view of Sung (US 5,174,857).
(Re Claim 4) wherein steps of forming the two first trenches comprises: forming a dielectric material (102) covering the wafer, wherein the first metal connection (104, 106) is disposed within and on the dielectric material (102), and the test structure (TE) is disposed within and on the dielectric material; forming a first photoresist (PR1) covering the dielectric material; performing a first lithographic process (Fig. 2B, col 4 lines 16-25), wherein the first lithographic process comprises patterning the first photoresist (Fig. 2B); etching the dielectric material to form the two first trenches by using the first photoresist after patterning as a mask (Fig. 2C), wherein the two first trenches divide the dielectric material into the first dielectric layer and the dielectric layer (Fig. 2C); and removing the first photoresist (Fig. 2D).
While Chen discloses using photolithography to pattern the photoresist PR1 to form the trenches in the photoresist layer PR1, Chen does not recite using a photo mask having corresponding patterns, however this would be obvious to any PHOSITA in light of Chen’s disclosure. Related art from Chang shows how a conventional photolithography process works (Fig. 2, ¶14) wherein a photo mask 70 having patterns 70a is used to expose a photoresist 60, thereby transferring the patterns in the mask to the resist layer 61. The use of photo masks having patterns in photolithography processes is considered well known in the art. A PHOSITA would find it obvious to use a photo mask, as taught by Chang, having corresponding patterns, in Chen’s disclosed lithography process since this is how conventional photolithography works.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. and Wei as applied above, and further in view of Arita et al. (US 2008/0128694), newly cited.
(Re Claim 7) further comprising a plurality of the first dice (D), a plurality of the second dice (D), a plurality of the scribe lines (SLR), a plurality of the test structures (TE) and more than two of the first trenches disposed on the wafer, wherein during the plasma process (Figs. 2B-2C), more than two of the second trenches are formed to respectively penetrate the wafer, and each of the second trenches respectively connects to a corresponding one of the first trenches.
While Chen only depicts a small, zoomed in portion of the much larger wafer, noting the wavy break lines throughout the figures, it is understood to comprise a large number of dies formed in a grid/array with corresponding dicing lines and test structures between the dies. For example, Arita shows a conventional wafer layout in Figs. 2-3 including a plurality of dies arranged in a grid/array and corresponding dicing lines and test structures between the dies and covering the entire wafer. It is obvious Chen’s wafer has a similar layout to Arita as this is conventional in the art.
Claims 1 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Arita et al. (US 2008/0128694, newly cited) in view of Mikami et al. (US 2020/0144095, newly cited), and Liu et al. (US 2016/0204071), of record.
(Re Claim 1) Arita teaches a method of dicing a wafer, comprising (see Figs. 4-8C and ¶¶76-99):
providing a wafer (1) with a front side and a back side, wherein a first die, a second die and a scribe line are disposed on the front side of the wafer (dies 2, scribe lines R2), the scribe line is positioned between the first die and the second die (Figs. 3-4), a test structure (3) and a dielectric layer (54) are disposed on the scribe line, wherein the test structure is disposed on the dielectric layer (Fig. 4), the first die comprises a first dielectric layer (52), two first trenches are respectively disposed within the dielectric layer at two sides of the test structure and the wafer is exposed through the two first trenches (Fig. 4);
performing a plasma process, wherein the plasma process comprises: etching the back side of the wafer to form two second trenches respectively penetrating the wafer, wherein each of the two second trenches respectively connects to a corresponding one of the two first trenches (Fig. 7D).
Arita lacks details of the die comprising a first metal connection disposed within and on the first dielectric layer, and providing a grinding tape covering the front side of the wafer and contacting the test structure, and planarizing the back side of the wafer to thin the wafer prior to performing the plasma process.
A PHOSITA would recognize Arita’s generic device regions 2 represented by the rectangles 53 are typically more complex, multilayer structures and would be motivated to look to related art to provide additional details of real devices where Arita is silent. Related art from Liu shows additional details of conventional device regions (II-III in Figs. 3-8), comprising insulating layers 300 and metal interconnects 301 (¶¶28-32). Modern integrated circuits use multilayer interconnect structures to maximize transistor density and manage heat dissipation by stacking circuitry in 3D. Employing multilayer interconnect structures would be obvious to include in Arita’s devices to provide the necessary connections/routing for the devices in a compact area. A PHOSITA would find it obvious to include interconnect structures as taught by Liu for the purpose of providing necessary connections between the devices in the integrated circuits.
Arita is silent regarding the grinding tape and planarizing the wafer. A PHOSITA would recognize the advantages of thinning semiconductor device wafers as this improves electrical performance, enhances heat dissipation, and enables compact, 3D-stacked packaging, ultimately allowing for smaller, lighter, and more reliable high-performance electronic devices. In addition, in a process flow such as Arita’s, thinning the wafer first will also advantageously reduce the required plasma dicing time. Related art from Mikami teaches a similar process flow wherein a grinding tape 3 is attached to the front side of the device wafer and also contacts the structures (unlabeled) in the dicing lines 5 (Fig. 1C), corresponding to Arita’s test structures. Mikami then performs a planarization step to thin the wafer (Fig. 2A, ¶53), then the wafer is plasma etched from the back side (Figs. 4A-4B) just as Arita does in Fig. 7D. A PHOSITA would find it obvious to integrate a wafer thinning process into Arita’s process for the known advantages of thinning the device wafer as discussed above. Mikami provides a suitable process that is compatible with and easy to integrate into Arita’s existing process. At Fig. 7A, Arita’s tape 4 may be substituted for Mikami’s tape 3, the wafer is then thinned from the backside (Mikami Fig. 2A), then the wafer can be subsequently plasma etched while still attached to the grinding tape (Mikami Fig. 4A, Arita Fig. 7D with Mikami’s grinding tape 3), thereby avoiding the need for additional tape transfer steps. After the plasma dicing, the dies can be transferred to a new tape (Mikami Figs. 6A-6B corresponding to Arita Fig. 8B) and the grinding tape removed (Mikami Fig. 6C corresponding to Arita Fig. 8C). A PHOSITA would find it obvious to modify Arita’s process to include Mikami’s steps of applying a grinding tape and performing the thinning to form thin semiconductor device devices, the grinding tape can be used for subsequent processes and removed after transferring to a new tape after singulation.
(Re Claim 6) wherein an etchant gas used in the plasma process comprises SF6, CF4/O2, CF2Cl2, CF3Cl, SF6/O2/Cl2, Cl2/H2/C2F6/CCl4, C2ClF5/O2, SiF4/O2, NF3, ClF3, CCl4, CCl3F5, C2ClF5/SF6, C2F6/CF3Cl, Br2 or CF3Cl/Br2 (¶71).
(Re Claim 7) further comprising a plurality of the first dice, a plurality of the second dice, a plurality of the scribe lines, a plurality of the test structures and more than two of the first trenches disposed on the wafer, wherein during the plasma process, more than two of the second trenches are formed to respectively penetrate the wafer, and each of the second trenches respectively connects to a corresponding one of the first trenches (see Figs. 1-3 regarding pluralities).
(Re Claim 8) wherein during the plasma process, the test structure is not removed (Fig. 7D).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Arita et al., Mikami et al., and Liu et al. as applied above, and further in view of Nakamura (US 2008/0220591), newly cited.
(Re Claim 3) further comprising: after the plasma process, providing a tape attached to the back side of the wafer (Arita Fig. 8B tape 6, ¶97); after attaching the tape to the back side of the wafer, removing the grinding tape (Arita Fig. 8C, as modified above, this step removes Mikami’s tape 3).
Arita is silent with respect to extending the tape to increase a distance between the first die and the second die and removing the first die and the second die from the tape. A PHOSITA would recognize these are obvious, well known, and conventional steps performed following a singulation process. The tape expansion makes it easier to pick dies from the tape without damaging/chipping adjacent dies while picking dies from the tape allows for subsequent testing, binning, sorting, and packaging processes to take place for each singulated die. A PHOSITA and may be motivated to look to related dicing art to teach these obvious steps. Related art from Nakamura teaches after dicing, the tape can be expanded and then dies are picked from the tape (Figs. 11B-12). Mikami also teaches the conventional step of picking the singulated dies from the tape after dicing (Fig. 7B). A PHOSITA would find it obvious to use an expandable tape as taught by Nakamura, then expanding the tape to increase distances between the dies to avoid damaging dies when picking the dies from the tape as taught by Nakamura and Makami.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 recites the allowable subject matter “…performing a second lithographic process, wherein the second lithographic process comprises patterning the second photoresist by the photo mask…” as set forth in the claimed combination. The closest prior art is Chen et al. and Chen does not use the same photo mask (photo mask introduced in claim 4) when patterning the second photoresist in Fig. 2L.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related devices, interconnect structures and seal rings, dicing, grinding/thinning, tape expansion, and picking processes.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898