DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 12 rejected, claims 13 through 18 withdrawn
Present action: claims 1 through 12 rejected, claims 13 through 18 withdrawn
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Uzoh (US 2024/0071915)
Regarding claim 1.
Uzoh teaches:
A semiconductor device structure (fig 3c:120; [para 0053]), comprising: a first substrate (fig 3c:104; [para 0041,0053]);
and a second substrate (fig 3c:104’; [para 0041,0053]) attached to the first substrate (fig 3c:104; [para 0041,0053]) by a hybrid bond structure (fig 3c:108; [para 0042,0043]), wherein the hybrid bond structure comprises:
a dielectric structure (fig 3c:106,106’; [para 0047,0053]) comprising a first dielectric layer (fig 3c:106; [para 0047]) formed above the first substrate (fig 3c:104; [para 0041,0053]) and a second dielectric layer (fig 3c:106’; [para 0047,0053]) bonded on the first dielectric layer (fig 3c:106; [para 0047,0053]);
and a conductive structure (fig 3c:122; [para 0047,0053]) comprising a first conductive layer (fig 3c:110; [para 0047,0053]) penetrating through the first dielectric layer (fig 3c:106; [para 0047,0053])and a second conductive layer (fig 3c:110’; [para 0047,0053]) formed at the second dielectric layer (fig 3c:106’; [para 0047,0053]), wherein the first dielectric layer (fig 3c:106; [para 0047,0053]) has a first opening and the second dielectric layer (fig 3c:106’; [para 0047,0053]) has a second opening;
wherein the first dielectric layer (fig 3c:106; [para 0047,0053]) and the second dielectric layer (fig 3c:106’; [para 0047,0053]) are bonded to form an air gap (fig 3c:304; [para 0047,0053]) by the first opening and the second opening.
Regarding claim 3.
Uzoh teaches the semiconductor device structure of claim 1, further
Uzoh teaches:
the second conductive layer (fig 3c:110’; [para 0047,0053]) is bonded to the first conductive layer (fig 3c:110; [para 0047,0053]) when the first dielectric layer (fig 3c:106; [para 0047,0053]) and the second dielectric layer (fig 3c:106’; [para 0047,0053]) are bonded together (fig 3c:108; [para 0042,0043]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2024/0071915) as applied to claim 3 and further in view of Chou (US 2014/0264948)
Regarding claim 4
Uzoh teaches the semiconductor device structure of claim 3, above
Uzoh teaches:
, wherein the first conductive layer (fig 3c:110; [para 0047,0053]) penetrates the first dielectric layer (fig 3c:106; [para 0047]), wherein the air gap (fig 3c:304; [para 0047,0053])is embedded in the first dielectric layer (fig 3c:106; [para 0047]) and the second dielectric layer (fig 3c:106’; [para 0047,0053]) and is sealed by and the second substrate (fig 3c:104’; [para 0041,0053]).
Uzoh does not teach a passivation between the hybrid bond structure and the first substrate and in contact with the first dielectric layer
Chou teaches:
a passivation layer (fig 5:108; [para 0009]) disposed between the hybrid bond structure (fig 10; [para 0023]) and the first substrate (fig 5:102; [para 0009]) and in contact with the first dielectric layer (fig 5:110; [para 0012]), wherein the first conductive layer (fig 5:112,106; [para 0012]) penetrates the passivation layer (fig 5:108; [para 0009]) and the first dielectric layer (fig 5:110; [para 0012]), wherein the air gap (fig 5,10:116; [para 0015]) is embedded in the first dielectric layer (fig 5:110; [para 0012]) and the second dielectric layer (fig 10:216; [para 0024]) and is sealed by the passivation layer (fig 5:108; [para 0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed to provide a passivation layer between the hybrid bond structure and the first substrate in order to enable the first substrate to comprise interconnect for connection to devices (paragraph 9).
Regarding claim 7.
Uzoh in view of Chou teaches the semiconductor device structure of claim 4, further:
Chou teaches
a material of the passivation layer (low-k dielectric, fig 5:108; [para 0009]) is different from a material of the dielectric structure (SiON SiN, fig 5:110; [para 0012]).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2024/0071915) in view of Chou (US 2014/0264948) as applied to claim 4 and further in view of Chen (US 2020/0395339).
Regarding claim 5.
Uzoh in view of Chou the semiconductor device structure of claim 4, above
Uzoh in view of Chou does not teach the first conductive layer is continuously tapered toward the first substrate.
Chen teaches:
the first conductive layer (fig 1e:120; [para 0026]) is continuously tapered toward the first substrate (fig 1e:102; [para 0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to taper the conductive layer in order to increase the contact area and thereby reduce contact resistance and facilitate alignment.
Regarding claim 6.
Uzoh in view of Chou in view of Chen teaches the semiconductor device structure of claim 5, further
Chen teaches:
the second conductive layer (fig 1e:220; [para 0030]) is tapered toward the second substrate (fig 1e:202; [para 0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to taper the conductive layer in order to increase the contact area and thereby reduce contact resistance and facilitate alignment.
Claim(s) 1, 8, 9, 10, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0216167) in view of Chen (US 2020/0395339)
Regarding claim 1.
Yang teaches:
A semiconductor device structure, comprising:
a hybrid bond structure (fig 11g:700; [para 0039]), wherein the hybrid bond structure (fig 11g:700; [para 0039]) comprises:
a dielectric structure (fig 11g:16; [para 0039]) comprising a first dielectric layer (fig 11g:16; [para 0039]) and a second dielectric layer (fig 11g:16; [para 0039]) bonded on the first dielectric layer (fig 11g:16; [para 0039]);
and a conductive structure comprising a first conductive layer (fig 11g:12,20,22; [para 0025,0039]) penetrating through the first dielectric layer (fig 11g:16; [para 0039]) and a second conductive layer (fig 11g:12,20,22; [para 0025,0039]) formed at the second dielectric layer (fig 11g:16; [para 0039]), wherein the first dielectric layer (fig 11g:16; [para 0039]) has a first opening (fig 11g:34; [para 0041]) and the second dielectric layer (fig 11g:16; [para 0039]) has a second opening (fig 11g:34; [para 0041]);
wherein the first dielectric layer (fig 11g:16; [para 0039]) and the second dielectric layer (fig 11g:16; [para 0039]) are bonded to form an air gap (fig 11g:26; [para 0039]) by the first opening (fig 11g:34; [para 0041]) and the second opening (fig 11g:34; [para 0041]).
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Yang does not teach a first and a second substrate.
Chen teaches:
A semiconductor device structure (fig 1e:10; [para 0031]), comprising: a first substrate (fig 1e:102; [para 0016]);
and a second substrate (fig 1e:202; [para 0029]) attached to the first substrate (fig 1e:102; [para 0016]) by a hybrid bond structure (fig 1e:15; [para 0032]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide substrates attached to the bonding structure in order that the bonding structure can be used to construct a semiconductor device.
Regarding claim 8.
Yang in view of Chang teaches the semiconductor device structure of claim 1, further
Yang teaches:
the air gap (fig 11g:26; [para 0039])comprises a first terminal portion defined within the first opening of the first dielectric layer (fig 11g:16; [para 0039]), and a neck portion in communication with the first terminal portion, and an aperture of the first terminal portion is different from an aperture of the neck portion.
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Regarding claim 9.
Yang in view of Chang teaches the semiconductor device structure of claim 8, further
Yang teaches:
the air gap (fig 11g:26; [para 0039]) further comprises a second terminal portion defined within the second opening of the second dielectric layer (fig 11g:16; [para 0039]), and in communication with the neck portion.
Regarding claim 10.
Yang in view of Chang teaches the semiconductor device structure of claim 9, further
Yang teaches:
the first terminal portion is partially misaligned with the second terminal portion (fig 11g; [para 0049]).
Regarding claim 11.
Yang in view of Chang teaches the semiconductor device structure of claim 1, further
Yang teaches:
the conductive structure (fig 11g:22,20,12; [para 0025,0039]) comprises a first segment (fig 11g: 12; [para 0025,0039]) and a second segment (fig 11g:22,20; [para 0025,0039]), the first segment (fig 11g: 12; [para 0025,0039]) has a first dimension, and the second segment (fig 11g:22,20; [para 0025,0039]) has a second dimension different from the first dimension.
Regarding claim 12.
Yang in view of Chang teaches the semiconductor device structure of claim 1, further
Chen teaches:
the first substrate (fig 1e:102; [para 0016]) comprises a memory device (; [para 0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the substrate to comprise a memory device so that information can be stored and used.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2023/0122531)
Regarding claim 1.
Uzoh teaches:
A semiconductor device structure (fig 11:4; [para 0036]), comprising: a first substrate (fig 11:80; [para 0036]);
and a second substrate (fig 11:70; [para 0036]) attached to the first substrate (fig 11:80; [para 0036]) by a hybrid bond structure (fig 11:79; [para 0036]), wherein the hybrid bond structure comprises: a dielectric structure (fig 11:83,74; [para 0036]) comprising a first dielectric layer (fig 11:83; [para 0036]) formed above the first substrate (fig 11:80; [para 0036]) and a second dielectric layer (fig 11:74; [para 0036]) bonded (fig 11:79; [para 0036]) on the first dielectric layer (fig 11:83; [para 0036]);
and a conductive structure (fig 11:84,86; [para 0036]) comprising a first conductive layer (fig 11:84; [para 0036]) penetrating through the first dielectric layer (fig 11:83; [para 0036]) and a second conductive layer (fig 11:86; [para 0036]) formed at the second dielectric layer (fig 11:74; [para 0036]), wherein the first dielectric layer (fig 11:83; [para 0036]) has a first opening (fig 11:85; [para 0036]) and the second dielectric layer (fig 11:74; [para 0036]) has a second opening (fig 11:87; [para 0036]);
wherein the first dielectric layer (fig 11:83; [para 0036]) and the second dielectric layer (fig 11:74; [para 0036]) are bonded to form an gap by the first opening (fig 11:85; [para 0036]) and the second opening (fig 11:87; [para 0036]).
Uzoh does not teach that the gap is an air gap
Uzoh teaches a second embodiment:
The isolation gap (fig 2:16; [para 0023])comprises an air gap (; [para 0023])
It would have been obvious to one before the effective filing date of the claimed invention for the gap to be an air gap due to the low dielectric constant of air which will reduce electric permittivity and coupling (paragraph 23)
Regarding claim 2.
Uzoh teaches the semiconductor device structure of claim 1, further
Uzoh teaches:
the air gap (fig 2:16; [para 0023]) is spaced apart from the conductive structure (fig 2:14; [para 0023]) by the dielectric structure (fig 2:12; [para 0023]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not anticipate amended elements of the claims.
However, newly applied rejections Uzoh (US 2024/0071915), Yang (US 2022/0216167) in view of Chen (US 2020/0395339), and Uzoh (US 2023/0122531) teach all elements of the amended claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817
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