CTNF 18/421,111 CTNF 97667 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Group I, claims 1-15 in the reply filed on 04/17/2026 is acknowledged. Claims 16-20 are canceled; Claims 21-25 are newly added. Claims 1-15 and 21-25 have been fully considered in Examination. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA 6. Claim s 1, 9-10, and 21-23 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chern (U.S. PG Pub No US2021/0091245A1) . Regarding claim 1, Chern teaches a method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059], comprising: receiving a substrate (1a-1c with 10) fig. 3J [0039, 0045], wherein the substrate (1a-1c with 10) has a dielectric layer (10) fig. 3J [0045] and a semiconductor layer (1c) fig. 3A [0039] (silicon [0039], described by [0019, 0039] of Chern as an intrinsic semiconductor) over (above at least portions of) the dielectric layer (10); forming a p-type doped region (DR1-L) fig. 3B [0040] (first conductivity type may be p-dopant [0040]) and an n-type doped region (DR2-L) fig. 3D [0042-0043] (second conductivity type may be n-dopant [0042]) in the semiconductor layer (1c); partially removing [see figs. 3L-3N, 0046-0047] the semiconductor layer (1c) and the dielectric layer (10) to form a recess (R) fig. 3N [0047] exposing portions of the p-type doped region (DR1-L) and the n-type doped region (DR2-L); and forming a photo-sensing structure (3) fig. 3P [0050] (‘photosensitive member’ [0050]) over (above at least portions of) sidewalls of the recess (R), wherein the photo-sensing structure (50) is spaced apart (vertically spaced by a thickness of 6) fig. 3P [0050] from a bottom (bottommost surface of R) of the recess (R). Regarding claim 9, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 1. Chern also teaches wherein the photo-sensing structure (3) fig. 3P [0050] extends past (beyond) a top surface (3 extends vertically beyond a top of) and a bottom surface (3 extends horizontally beyond a bottom of) of the p-type doped region (DR1-L) fig. 3B [0040]. Regarding claim 10, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 1. Chern also teaches wherein the photo-sensing structure (3) fig. 3P [0050] and the dielectric layer (10) fig. 3J [0045] together surround a lower portion (LP; a select portion of R in a lower half of R, as defined in annotated fig. 3Z below ) of the recess (R) fig. 3N [0047], and the lower portion of the recess (R) is an enclosed space (enclosed by surrounding portions of 3, as defined in annotated fig. 3Z below ). [AltContent: arrow] [AltContent: textbox (LP)] [AltContent: rect] PNG media_image1.png 882 1381 media_image1.png Greyscale Annotated fig. 3Z of Chern Regarding claim 21, Chern teaches a method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059], comprising: forming a p-type doped structure (DR1-L) fig. 3B [0040] (first conductivity type may be p-dopant [0040]) and an n-type doped structure (DR2-L) fig. 3D [0042-0043] (second conductivity type may be n-dopant [0042]) over a substrate (1a-1c with 10) fig. 3J [0039, 0045]; and forming a photo-sensing structure (3) fig. 3P [0050] (‘photosensitive member’ [0050]) over sidewalls of the p-type doped structure (DR1-L) and the n- type doped structure (DR2-L), wherein there is an enclosed trench (trench portion in 1c, filled by 6) fig. 3Z [0060, 0048] formed (vertically) between the substrate (1a-1c with 10) fig. 3J [0039, 0045] and the photo-sensing structure (3) after the photo-sensing structure (3) is formed (in completed structure of fig. 3Z). Regarding claim 22, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 21. Chern also teaches further comprising: forming a recess (R) fig. 3N [0047] exposing sidewalls of the p-type doped structure (DR1-L) fig. 3B [0040] and the n-type doped structure (DR2-L) fig. 3D [0042-0043]; and epitaxial growing [0050] a semiconductor material (3) fig. 3P [0050] (intrinsic germanium [0050, 0019, 0017]) on the sidewalls of the p-type doped structure (DR1-L) and the n-type doped structure (DR2-L) to form the photo-sensing structure (3). Regarding claim 23, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 22. Chern also teaches wherein the recess (left sidewall of R) fig. 3N [0047] vertically extends across (‘across’ interpreted as ‘over’) a topmost surface of the p-type doped structure (DR1-L) fig. 3M [0040] (R is formed extending over/through a topmost surface of DR1-L in fig. 3M) and a bottommost surface of the n-type doped structure (DR2-L) fig. 3N [0042-0043] (right sidewall of R extends vertically over bottommost surface of DR2-L) . 07-15 AIA Claim s 11-15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chiang (U.S. PG Pub No US2022/0131017A1) . Regarding claim 11, Chiang teaches a method [see figs. 10-18, 0009, 0036-0038] for forming a semiconductor device structure (1900) fig. 19 [0059], comprising: forming a p-type doped structure (518) fig. 11 [0034] and an n-type doped structure (510) fig. 11 [0034] over (at least partially above) a dielectric layer (comprising left STI region, denoted by 1002 in fig. 10, filled by low k dielectric material [0033]) fig. 10 [0033]; and forming a photo-sensing structure (1402) fig. 14A [0037-0038] (‘photodiode’ [0038] ‘to measure or detect (sense) light’ [0018]) over (at least partially above) sidewalls of the p-type doped structure (518) and the n- type doped structure (510), wherein the photo-sensing structure (1402) and the dielectric layer (1002/310) fig. 19 [0035] (left ‘dielectric layer’ 1002 has been converted/expanded into a single 310 multi-sublayer material at stage shown in fig. 12 [0033, 0035]) together surround an enclosed trench (trench 1302 [0037] in 300, formed in 300 in fig. 13, is enclosed and surrounded by collective combination of 1402/309 [0042], 310/1002 material, 300 material, and 530 material in finished structure shown in fig. 19 ). Regarding claim 12, Chiang teaches the method [see figs. 10-18, 0009, 0036-0038] for forming a semiconductor device structure (1900) fig. 19 [0059] as claimed in claim 11. Chiang also teaches further comprising forming a semiconductor cap (1502 with 1602) fig. 15A, fig. 16A [0039-0040] (comprising silicon germanium material 1502 and silicon material 1602) [0039-0040] directly on the photo-sensing structure (1402) fig. 14A [0037-0038]. As evidence that silicon is widely recognized as a semiconductor material Chern (U.S. PG Pub No US2021/0091245A1), see [0019, 0025] of Chern – wherein Chern describes silicon and germanium as “intrinsic semiconductors”. Regarding claim 13, Chiang teaches a method [see figs. 10-18, 0009, 0036-0038] for forming the semiconductor device structure (1900) fig. 19 [0059] as claimed in claim 12. Chiang also teaches, wherein the semiconductor cap (1502/528 with 1602/526) fig. 16A [0039-0041] (1502 becomes 528 in fig. 17; 1602 becomes 526 in fig. 17 [0041]) is (at least partially) p-type doped (left portions of 1502/528 with 1602/526 in 520 p-doped region 520 are p-doped [see fig. 17, 0041]). Regarding claim 14, Chiang teaches the method [see figs. 10-18, 0009, 0036-0038] for forming a semiconductor device structure (1900) fig. 19 [0059] as claimed in claim 12. Chiang also teaches further comprising: forming a dielectric protective element (530) fig. 18 [0042] (may be formed of a high-k dielectric material) [0042] over (at least partially above) the semiconductor cap (1502/528 with 1602/526) fig. 16A [0039-0041], wherein the dielectric protective element (530) extends past (horizontally beyond) a first interface (border of respective sidewalls) between the photo-sensing structure (1402/309) fig. 18 [0039, 0042] and the p-type doped structure (518) fig. 18 [0034] and a second interface (border of respective sidewalls) between the photo-sensing structure (1402/309) fig. 18 [0039, 0042] and the n-type doped structure (510) fig. 18 [0034]. Regarding claim 15, Chiang teaches the method [see figs. 10-18, 0009, 0036-0038] for forming a semiconductor device structure (1900) fig. 19 [0059] as claimed in claim 11. Chiang also teaches wherein the p-type doped structure (518) fig. 11 [0034] and the n-type doped structure (5108) fig. 11 [0034] are formed in a semiconductor layer (silicon layer of 300) fig. 19 [0033-0034], and the method further comprises: partially removing [see fig. 13, 0036] the semiconductor layer (300) and the dielectric layer (1002/310) fig. 12 [0035] (left ‘dielectric layer’ 1002 has been converted/expanded into a single 310 multi-sublayer material at stage shown in fig. 12 [0033, 0035]) to form a recess (entire 1302) fig. 13 [0036] extending into (through) the dielectric layer (310), wherein a lower portion of the recess (1302) forms the enclosed trench (portion of 1302 in 300) after the (completed) formation of the photo-sensing structure (1402/309) fig. 18 [0039, 0042] (trench 1302 [0037] in 300, formed in 300 in fig. 13, is enclosed and surrounded by collective combination of 1402/309 [0042], 310/1002 material, 300 material, and 530 material in finished structure shown in fig. 19 ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chern (U.S. PG Pub No US2021/0091245A1), as applied in claim 1 above, in view of Chiang (U.S. PG Pub No US2022/0131017A1) . Regarding claim 2, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 1. However, Chern does not explicitly disclose further comprising: forming a semiconductor cap over the photo-sensing structure (3) fig. 3P [0050]. Chiang teaches a method [see figs. 10-18, 0009, 0036-0038] for forming a semiconductor device structure (1900) fig. 19 [0059] further comprising: forming a semiconductor cap (1602) fig. 15A, fig. 16A [0039-0040] (comprising silicon material 1602) [0039-0040] ( [0019, 0025] of Chern teaches that silicon is a semiconductor material) over the photo-sensing structure (1402) fig. 14A [0037-0038]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Chern to include the in-situ formation of the semiconductor cap layer(s) [0037-0041] of Chiang over the photo-sensing structure in order to protect the underling germanium photosensing structure from crystalline damage [0040], erosion [0040], and oxidation [0041] during processing [0040-0041], thereby reducing leakage current [0040] and dark current [0041] of the finished product [0040-0041], as taught by Chiang . Regarding claim 3, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 2. Chern in view of Chiang (with reference to Chiang ) also teaches wherein the photo-sensing structure (1402/309) fig. 14A [0037, 0041] and the semiconductor cap (1602/526) fig. 16A [0039-0041] (1602 becomes 526 in fig. 17 [0041]) are epitaxially grown in-situ [0038-0040] in a process chamber (grown in-situ same chamber [0038-0040]), and vacuum of the process chamber is not broken (chamber is maintained as a vacuum with respect to oxygen [0038] during in-situ growth such that oxidation does not occur [0038] and chamber is not exposed to the pressure of ambient environment [0038]) during the growth of photo-sensing structure (1402/309) fig. 14A [0037-0038] and the semiconductor cap (1602) fig. 16A [0039-0041]. Regarding claim 4, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 3. Chern in view of Chiang (with reference to Chiang ) also teaches further comprising: epitaxial growing [0039] a silicon germanium layer (1502) fig. 15A [0039] on the photo-sensing structure (1402/309) fig. 14A [0037, 0041] before the formation of the semiconductor cap (1602) fig. 16A [0040]. Regarding claim 5, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 4. Chern in view of Chiang (with reference to Chiang ) also teaches wherein the silicon germanium layer (1502) fig. 15B [0039] has an atomic concentration of germanium [0039], and the atomic concentration of germanium gradually decreases [0039] along a direction from a bottom of the silicon germanium layer (1502) towards the semiconductor cap (1602) fig. 16A [0040] (silicon:germanium ratio may ‘change over thickness’ of 1502 [0039] (implying gradual decrease or increase over thickness of 1502– may transition from germanium heavy near germanium layer 1402 [0039] to silicon heavy near silicon cap 1602 [0039], such that germanium concentration decreases from bottom to top [0039]). Regarding claim 6, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 2. Chern in view of Chiang (with reference to Chiang ) also teaches further comprising: forming a dielectric stressor layer (530) fig. 18 [0042] (formed of high-k dielectric material such as Al2O3 that induces some non-zero degree of stress in 526 through non-zero weight of 530) over the semiconductor cap (1602/526) fig. 17 [0041]. Regarding claim 7, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 6. Chern in view of Chiang (with reference to Chiang ) also teaches the dielectric stressor layer (530) fig. 18 [0042] extends past (beyond) opposite edges of the photo-sensing structure (309) fig. 18 [0041] Regarding claim 8, Chern in view of Chiang teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 6. Chern in view of Chiang (with reference to Chiang ) the semiconductor cap (526/1602) fig. 17 [0041] is a silicon layer [0041] doped with p-type dopants (in 520 region of 526) fig. 17 [0042] . 07-21-aia AIA Claim s 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chern (U.S. PG Pub No US2021/0091245A1), as applied in claim 21 above, in view of Usami (U.S. PG Pub No US2017/0317221A1) . Regarding claim 24, Chern teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 21. However, Chern does not explicitly disclose wherein the photo-sensing structure (3) fig. 3P [0050] is formed to have a curved bottom (flat bottom instead). Usami teaches a method [0108] for forming a semiconductor device structure [see fig. 20, 0104] wherein the photo-sensing structure (IGL of PD5) fig. 20 [0104-0106] is formed to have a curved bottom (round shape [0104]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Chern such that the opening in which the photodiode is formed is formed to have a rounded bottom [0104-0107, 0109-0111] in order to improve control of the epitaxial growth of the germanium photo sensing structure [0109-0111] within the confines of the trench [0111], as taught by Usami . Regarding claim 25, Chern in view of Usami teaches the method [see figs. 3A-3Z, 0009, 0036-0038] for forming a semiconductor device structure (100) fig. 3Z [0059] as claimed in claim 21. Chern in view of Usami (with reference to Usami ) also teaches wherein a center portion of the curved bottom of the photo-sensing structure (3) fig. 20 [0104-0107] is formed tIo be closer to the substrate (SUB) fig. 20 [0041] than an edge portion (upper portions of peripheral portions of bottom of 3 curved away from SUB) of the curved bottom of the photo-sensing structure (3) fig. 20 [0104] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chern (U.S. PG Pub No US2021/0091239A1) and Chiang (U.S. PG Pub No US2023/0299217A1) teach other examples of an epitaxial photosensing structures formed in trench/recess of substrate. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/12/2026 Application/Control Number: 18/421,111 Page 2 Art Unit: 2892 Application/Control Number: 18/421,111 Page 3 Art Unit: 2892 Application/Control Number: 18/421,111 Page 4 Art Unit: 2892 Application/Control Number: 18/421,111 Page 5 Art Unit: 2892 Application/Control Number: 18/421,111 Page 6 Art Unit: 2892 Application/Control Number: 18/421,111 Page 7 Art Unit: 2892 Application/Control Number: 18/421,111 Page 8 Art Unit: 2892 Application/Control Number: 18/421,111 Page 9 Art Unit: 2892 Application/Control Number: 18/421,111 Page 10 Art Unit: 2892
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