CTNF 18/421,176 CTNF 100849 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Species B, claims 1-4, 6, 12-15, and 21-23 in the reply filed on 04/03/2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/06/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim 21 is rejected under 35 U.S.C. 102 as being anticipated by Kim et al.( US 2022/0416086 A1; hereinafter Kim ) Regarding claim 21 , Kim teaches a semiconductor structure, comprising: a transistor region having fin active regions ( [0024] first circuit fin 6a ) extending lengthwise along a first direction over a substrate ( Fig. 5a substrate 3 ), each of the fin active regions includes channel regions ( [0033] first channel layers 18a, 22a, and 26a ) between source/drain features ( [0031] Source/drain regions 46, 48, and 50 may include first source/drain regions 46 ); a filter region ( [0047] dummy fin 6c; Fig. 1 DA ) adjacent the transistor region ( Fig. 1 CA1 ) along a second direction perpendicular to the first direction ( as shown in Fig. 1 ), the filter region( Fig. 4 #6c) being free of active transistor devices ( [0020] the term “dummy region” denotes a region in which active element(s) are not disposed ) and having filter fins ( Fig. 4 #6c ) extending lengthwise along the first direction over the substrate ( Fig. 4 #3 ); and a gate structure ( Fig. 2A first gate structure 32a ) extending across the transistor region ( [0020] the term “circuit region” denotes a region in which active element(s) (e.g., transistors) are disposed ) and the filter region ( Fig. 4 #6c ) along the second direction ( as shown in Fig. 4 ), the gate structure ( Fig. 2A #32a ) having a gate electrode ( Fig. 2A #62a ) over a gate dielectric ( Fig. 2A #60a ), wherein the gate dielectric ( Fig. 2 #60a ) is disposed over channel regions ( Fig. 2 channel layers 18a, 22a, and 26a ) of the fin active regions in the transistor region ( Fig. 2A ) and over the filter fins in the filter region ( Fig. 4 #6c), wherein the filter fins have a first width along the second direction ( as shown in Fig. 4 ), the fin active regions have a second width along the second direction ( as shown in Fig. 2A ), and the first width is greater than the second width ( as shown in Fig. 2A) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wu et al.; US 2020/0075610 A1; 07/2019 Claim 1: Kim discloses a semiconductor structure, comprising: a first circuit area ( Fig. 1 CA1 ) having first fin ( [0024] first circuit fin 6a ) active regions extending lengthwise along a first direction ( as shown in Fig. 6a ) over a substrate ( Fig. 6a substrate 3 ), each of the first fin active regions includes first channel regions ( [0033] first channel layers 18 a , 22 a and 26 a ) between first source/drain features ( [0031] Source/drain regions 46, 48, and 50 may include first source/drain regions 46 ); a second circuit area having second fin ( [0024] second circuit fin 6b ) active regions extending lengthwise along the first direction ( as shown in Fig. 6b ) over the substrate ( Fig. 6b substrate 3 ), each of the second fin active regions includes second channel regions ( [0033] second channel layers 18 b , 22 b , and 26 b spaced apart and stacked on the second circuit lower barrier layer 12 b ) between second source/drain features ( [0031] second source/drain regions 48 spaced apart from in the vertical (Z) direction on the second circuit lower barrier layer 12 b ); a gate connector area ( [0046] The gate structures 32 a , 32 b , and 32 c may include a first gate structure 32 a , a second gate structure 32 b , and a dummy gate structure 32 c ) between and separating the first ( Fig. 8 #32a ) and the second circuit areas ( Fig. 10 #32b ), the gate connector area having filter fins ( [0047] dummy fin 6 c ) extending lengthwise along the first direction ( as shown in Figs. 8 and 10 ) over the substrate( Fig. 8 #3 and Fig. 10 #3 ); and a gate structure ( Fig. 10 #32a ) extending across the first circuit area ( Fig. 1 CA1 ), the gate connector area ( [0047] The first gate structure 32 a may include a portion intersecting the first circuit fin 6 a and extending in a second horizontal (or Y) direction perpendicular to the first horizontal (X) direction, to overlap the isolation layer 30. The second gate structure 32 b may a portion intersecting the second circuit fin 6 b and extending in the second horizontal (Y) direction to overlap the isolation layer 30 ), and the second circuit area ( Fig. 1 CA2 ) along a second direction perpendicular to the first direction ( as shown in Fig. 1 CA2 is oriented along the Y direction), the gate structure is disposed over the first and second channel regions ( as discussed above ) and over the filter fins ( Fig. 4 #32c over 6c ), wherein the gate structure includes a gate dielectric ( Fig. 2A first gate dielectric layer 60a ) over top and side surfaces of the first fin active regions ( [0051] The first gate 58 a may surround an upper surface, a lower surface, and a side surface of each of the first channel layers 18 a , 22 a , and 26 a and may extend in the second horizontal (Y) direction ), the second fin active regions ( Fig. 3A #18b, #22b, and #26b ), and the filter fins ( Fig. 4 6c). Kim does not appear to disclose a portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas. However, Wu teaches a portion of the gate structure in the gate connector area ( Fig. 1A gate structure GP0 ) has a greater resistivity ( Fig. 1E: resistor Rox, Rb0, and Rb1) than portions of the gate structure in the first ( Fig. 1A GR0 ) and the second circuit areas ( Fig. 1A GR1 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wu with Kim to implement a portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas because gate structures vary to balance electrical performance, fabrication feasibility, and layout efficiency. Claims 2 and 3 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wu et al.; US 2020/0075610 A1; 07/2019 as it relates to claim 1 above and further in view of Xie et al.; US 12,527,068 B2; 12/2021 Claim 2: Kim and Wu disclose the semiconductor structure of claim 1 ( as discussed above ). Neither Kim nor Wu appear to disclose the first fin active regions are spaced apart from each other by a first spacing along the second direction, the filter fins are spaced apart from each other by a second spacing along the second direction, and the first spacing is greater than the second spacing. However, Xie teaches the first fin active regions ( Fig. 10; Col. 6 lines 30 -35 a bi-layer portion of the first dielectric liner 325 under the active region ) are spaced apart from each other by a first spacing along the second direction ( as shown in Fig. 10 Y direction image ), the filter fins are spaced apart from each other by a second spacing along the second direction ( Fig. 10 X direction image ), and the first spacing is greater than the second spacing ( as shown in Fig. 10 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xie with Kim and Wu to implement the first fin active regions are spaced apart from each other by a first spacing along the second direction, the filter fins are spaced apart from each other by a second spacing along the second direction, and the first spacing is greater than the second spacing because the combination of electrical, geometric, and process driven constraints explain why fins are placed spaced apart. Claim 3: Kim, Wu, and Xie disclose the semiconductor structure of claim 1 ( as discussed above ). Neither Kim nor Wu appear to disclose the first fin active regions have a first width along the second direction, the filter fins have a second width along the second direction, and the second width is greater than the first width. However, Xie teaches the first fin active regions ( Fig. 10; Col. 6 lines 30 -35 a bi-layer portion of the first dielectric liner 325 under the active region ) have a first width along the second direction ( Fig. 10 #305 width in the X image ), the filter fins have a second width along the second direction ( Fig. 10 Y image ), and the second width ( Fig. 10 Y image under the far right ) is greater than the first width ( as shown in Fig. 10 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xie with Kim and Wu to implement the first fin active regions have a first width along the second direction, the filter fins have a second width along the second direction, and the second width is greater than the first width because this approach is used to ensure alignment precision and maintain process margins for vertical fin profiles. Claims 4 and 6 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wu et al.; US 2020/0075610 A1; 07/2019 as it relates to claim 1 above and further in view of Wang(‘851) et al.; US 2018/0374851 A1; 06/2017 Claim 4: Kim and Wu disclose the semiconductor structure of claim 1 ( as discussed above ). Neither Kim nor Wu appear to disclose the first and second channel regions are doped with a first dopant, the filter fins are doped with a second dopant, and the first and second dopants are opposite type dopants. However, Wang (‘851) teaches the first and second channel regions ( Fig. 12 #1224 ) are doped with a first dopant ( Fig. 12 channel region 1218 ), the filter fins ( Fig. 12 #1227 ) are doped with a second dopant ( Fig. 12 #1013 ), and the first ( [0059] For example, for a P-type FINFET, the channel region 1218 can be doped so as to have an N− conductivity; whereas, for an N-type FINFET, the channel region 1218 can be doped so as to have a P− conductivity. Alternatively, the channel region 1218 can be undoped ) and second dopants are opposite type dopants ( Fig. 12 #1013 is a single diffusion break so it is a different dopant than 1218 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang (‘851) with Kim and Wu to implement the first and second channel regions are doped with a first dopant, the filter fins are doped with a second dopant, and the first and second dopants are opposite type dopants because this approach is used to create depletion regions and control turn-on voltage and switching behavior. Claim 6: Kim, Wu, and Wang (‘851) disclose the semiconductor structure of claim 4 ( as discussed above ). Neither Kim nor Wu appear to disclose the source/drain features of the first fin active regions include epitaxial features of the second dopant, wherein each of the filter fins is free of epitaxial features. However, Wang (‘851) teaches the source/drain features of the first fin active regions ( Fig. 12 source/drain recesses 1212 ) include epitaxial features ( [0038] The mushroom top 1215, sometimes referred to as a T-top, will shadow portions of the substrate 101 during RIE, leaving sidewalls 1221, which provide silicon for epitaxial growth for the source/drain regions described below ) of the second dopant ( [0040] For example, for a P-type FINFET, the additional semiconductor layer can be in-situ doped with a P-type dopant so as to have P+ conductivity ), wherein each of the filter fins ( Fig. 12 #1227 ) is free of epitaxial features ( [0043] Lithographic patterning and etch processes can then be performed in order to form, from this gate stack, gate-first gates, each having a gate cap ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang (‘851) with Kim and Wu to implement the source/drain features of the first fin active regions include epitaxial features of the second dopant, wherein each of the filter fins is free of epitaxial features because this approach is used to establish the current carrying path and reduce parasitic resistance. Claims 12 and 13 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wang(‘851) et al.; US 2018/0374851 A1; 06/2017 Claim 12: Kim discloses a semiconductor structure, comprising: a transistor area ( Fig. 1 CA1 ) having fin active regions extending lengthwise along a first direction ( [0024] first circuit fin 6a ) over a substrate ( Fig. 5a substrate 3 ), each of the fin active regions includes channel regions ( [0033] first channel layers 18a, 22a, and 26a ) between source/drain features ( [0031] Source/drain regions 46, 48, and 50 may include first source/drain regions 46 ); a filter area ( [0047] dummy fin 6 c ; Fig. 1 DA ) adjacent the transistor area ( Fig. 1 CA1 ) along a second direction perpendicular to the first direction ( as shown in Fig. 1 ), the filter area having filter fins ( Fig. 4 #6c ) extending lengthwise along the first direction ( as shown in Fig. 4 ) over the substrate ( Fig. 4 #3 ); and a gate structure ( Fig. 2A first gate structure 32a ) having a gate dielectric (Fig. 2A first gate dielectric layer 60a ) and a gate fill metal ( Fig. 2A first gate electrode 62a ) over the gate dielectric ( Fig. 2A #60a ), the gate structure ( Fig. 2A #32a ) extends across the transistor area and the filter area along the second direction ( as shown in Fig. 1 ), and the gate structure ( Fig. 4 #32c ) is disposed directly over the channel regions ( Fig. 2A first channel layers 18c, 22c, and 26c ) of the fin active regions and directly over the filter fins ( Fig. 4 #6c ). Kim does not appear to disclose the source/drain features of the first fin active regions include epitaxial features, wherein each of the filter fins is free of epitaxial features. However, Wang (‘851) teaches the source/drain features of the first fin active regions ( Fig. 12 source/drain recesses 1212 ) include epitaxial features ( [0038] The mushroom top 1215, sometimes referred to as a T-top, will shadow portions of the substrate 101 during RIE, leaving sidewalls 1221, which provide silicon for epitaxial growth for the source/drain regions described below ), wherein each of the filter fins ( Fig. 12 #1227 ) is free of epitaxial features ( [0043] Lithographic patterning and etch processes can then be performed in order to form, from this gate stack, gate-first gates, each having a gate cap ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang(‘851) with Kim to implement the source/drain features of the first fin active regions include epitaxial features, wherein each of the filter fins is free of epitaxial features because the source/drain implementation overcomes lithography limitations. Claim 13: Kim and Wang (‘851 ) disclose the semiconductor structure of claim 12 ( as discussed above). Kim does not appear to disclose the channel regions and the source/drain features have opposite type dopants, wherein the channel regions have a first-type dopant, and the filter fins have a second-type dopant opposite the first-type dopant. However, Wang ( ‘851 ) teaches the channel regions ( Fig. 12 #1224 ) and the source/drain features ( Fig. 12 source/drain recesses 1212 ) have opposite type dopants ( [0066] As discussed above, for an N-type FINFET, the channel region can have P-type conductivity (or can be undoped) and the source/drain regions can have N-type conductivity ), wherein the channel regions have a first-type dopant ( [0059] For example, for a P-type FINFET, the channel region 1218 can be doped so as to have an N− conductivity ), and the filter fins ( Fig. 12 #1227 ) have a second-type dopant opposite the first-type dopant ( Fig. 12 #1013 is a single diffusion break so it is a different dopant than 1218 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang(‘851) with Kim to implement the channel regions and the source/drain features have opposite type dopants, wherein the channel regions have a first-type dopant, and the filter fins have a second-type dopant opposite the first-type dopant because aligning the channel along the direction of maximum carrier mobility improves conduction. Claim 14 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wang(‘851) et al.; US 2018/0374851 A1; 06/2017 as it relates to claim 12 above and further in view of Wu et al.; US 2020/0075610 A1; 07/2019 Claim 14: Kim and Wang (‘851) disclose the semiconductor structure of claim 12 ( as discussed above ). Neither Kim nor Wang (‘851) appear to disclose the gate structure includes a first gate portion within the transistor area and a second gate portion within the filter area, and the second gate portion has a greater resistivity than the first gate portion. However, Wu teaches the gate structure includes a first gate portion ( Fig. 1A gate structure GR0 ) within the transistor area ( transistor MNR0 ) and a second gate portion ( Fig. 1A GP0 ) within the filter area ( MNP0 ), and the second gate portion has a greater resistivity than the first gate portion ( Fig. 1E: resistor Rox, Rb0, and Rb1 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wu with Kim and Wang (‘851) to implement the gate structure includes a first gate portion within the transistor area and a second gate portion within the filter area, and the second gate portion has a greater resistivity than the first gate portion because the first gate portion establishes a predictable gate capacitance critical for high-speed performance. Claim 15 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wang(‘851) et al.; US 2018/0374851 A1; 06/2017 and Wu et al.; US 2020/0075610 A1; 07/2019 as it relates to claim 14 above and further in view of Wang(‘822) et al.; US 2026/0006822 A1; 10/2022 Claim 15: Kim, Wang ( ‘851 ), and Wu disclose the semiconductor structure of claim 14 ( as discussed above). Neither Kim nor Wang (‘851) nor Wu appear to disclose the first gate portion includes Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, or combinations thereof, wherein the second gate portion includes Ti, TiN, brass, phosphor bronze, cast steel, a metal compound, or a combination thereof. However, Wang (‘822) teaches the first gate portion ( Fig. 16 first gate electrode 20E ) includes Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, or combinations thereof ( [0106] Correspondingly, in the case of an N-type device, metals with a greater work function, such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MON, etc. with a greater work function obtained by adjusting the composition of the compound, may be used as a gate electrode material by the first gate electrode 20E ), wherein the second gate portion ( Fig. 16 second gate electrode 50E ) includes Ti, TiN, brass, phosphor bronze, cast steel, a metal compound, or a combination thereof ( [0106] a metal with a less work function, such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HIN, TIN, TaN, TaSiN, etc. with a less work function obtained by adjusting the composition of the compound, may be used as a gate electrode material by the second gate electrode 50E ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang (‘822) with Kim, Wang (‘851), and Wu to implement the first gate portion includes Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, or combinations thereof, wherein the second gate portion includes Ti, TiN, brass, phosphor bronze, cast steel, a metal compound, or a combination thereof because these materials facilitate multi-objective optimization for electrical, electronic, thermal/chemical, and fabrication. Claim 22 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Wu et al.; US 2020/0075610 A1; 07/2019 Claim 22: Kim discloses the semiconductor structure of claim 21 ( as discussed above). Kim does not appear to disclose the gate electrode of the gate structure in the filter region has a greater resistivity than the gate electrode of the gate structure in the transistor region. However, Wu teaches the gate electrode of the gate structure in the filter region ( Fig. 1A GP0 in MNP0 region) has a greater resistivity ( Fig. 1E: resistor Rox, Rb0, Rb1 ) than the gate electrode of the gate structure in the transistor region ( Fig. 1A gate structure GR0 in MNR0 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wu with Kim to implement the gate electrode of the gate structure in the filter region has a greater resistivity than the gate electrode of the gate structure in the transistor region because resistance in the filter impacts both switching speed and signal integrity. Claim 23 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0416086 A1; 04/2022 in view of Xie et al.; US 12,527068 B2; 12/2021 Claim 23: Kim discloses the semiconductor structure of claim 21 ( as discussed above). Kim does not appear to disclose a first spacing between fin active regions is greater than a second spacing between the filter fins. However, Xie teaches a first spacing ( as shown in Fig. 10 Y direction image ) between fin active regions ( Fig. 10; Col. 6 lines 30 -35 a bi-layer portion of the first dielectric liner 325 under the active region) is greater than a second spacing ( Fig. 10 X direction image ) between the filter fins (as shown in Fig. 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xie with Kim to implement a first spacing between fin active regions is greater than a second spacing between the filter fins because this is driven by fabrication process margins, mechanical stress management, and electrical performance considerations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.N.F./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/421,176 Page 2 Art Unit: 2817 Application/Control Number: 18/421,176 Page 3 Art Unit: 2817 Application/Control Number: 18/421,176 Page 4 Art Unit: 2817 Application/Control Number: 18/421,176 Page 5 Art Unit: 2817 Application/Control Number: 18/421,176 Page 6 Art Unit: 2817 Application/Control Number: 18/421,176 Page 7 Art Unit: 2817 Application/Control Number: 18/421,176 Page 8 Art Unit: 2817 Application/Control Number: 18/421,176 Page 9 Art Unit: 2817 Application/Control Number: 18/421,176 Page 10 Art Unit: 2817 Application/Control Number: 18/421,176 Page 11 Art Unit: 2817 Application/Control Number: 18/421,176 Page 12 Art Unit: 2817 Application/Control Number: 18/421,176 Page 13 Art Unit: 2817 Application/Control Number: 18/421,176 Page 14 Art Unit: 2817 Application/Control Number: 18/421,176 Page 15 Art Unit: 2817 Application/Control Number: 18/421,176 Page 16 Art Unit: 2817
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