CTNF 18/421,312 CTNF 71281 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group III (claims 16-20) and Species N (Fig. 3, claim 18) in the reply filed on 5/16/26 is acknowledged. Applicant also added new claims 21-35 and asserted they are drawn to Group III. Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the forming a pattern in the mask layer (or patterning a hard mask) of claims 16, 19-21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections 07-29-01 AIA Claim s 21-35 is/are objected to because of the following informalities: The new claims includes typographical errors. 21, 30: “resources” should be changed to --recesses-- The other claims are objected as being dependent on one of claims 21 and 30 . Appropriate correction is required. Specification 07-29 AIA The disclosure is objected to because of the following informalities: In paragraph [0062] of the application, as published, “458” should be changed to --258 --. Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-02-aia The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). 07-27-aia AIA Claim(s) 16 is/are rejected under 35 U.S.C. 102( a)(2 ) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over U.S. Patent Application Publication No. 2023/0066828 (Jang) . Jang discloses 16. (Original) A method comprising: forming a plurality of fin structures 404A - 404B on a substrate 302 along a first direction; forming a plurality of gate structures 1000 / 1020 across the plurality of fin structures 404A - 404D; depositing a mask layer 1403 over the plurality of gate structures 1000 / 1020; forming a pattern ([0061]) in the mask layer 1403, wherein the pattern comprises: a first opening 1400 in align with a first gate structure 1000 of the plurality of gate structures 1000 / 1020; and a second opening 1450 in align with the second gate structure 1020 of the plurality of gate structures 1000 / 1020, wherein the first gate structures 1000 and the second gate structure 1020 are immediately next to each other, the first opening 1400 has a first width along the first direction, the second opening 1450 has a second width along the first direction, and the first width is greater than the second width ([0059]-[0061]); forming a first isolation opening 1500 and a second isolation opening 1550 using the pattern in the mask layer ([0073]); and depositing a dielectric layer 1702 to fill the first isolation opening 1500 and the second isolation opening 1550. Even assuming arguendo that Jang does not explicitly disclose a first opening in align with a first gate structure and a second opening in align with the second gate structure, wherein the first gate structures and the second gate structure are immediately next to each other, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to do so based on the language in the below paragraphs. [0058]: dummy gate structures 1000 and 1020 are respectively cut, intercepted, or otherwise disconnected to form a gate cut trench 1400 in the I/O area 302A and a gate cut trench 1450 in the core area 302B (i.e., the openings are formed by cutting the gate structures) [0059]: the gate cut trenches 1400 and 1450 is formed across a certain portion of each of the dummy gate structures 1000 and 1020 (i.e., the opening is located on / through the gate structure) [0060]: remove a portion of the dummy gate 1004 and a portion of the dummy gate dielectric 1002 that are disposed over the dummy fin structure 600A and remove a portion of the dummy gate 1024 and a portion of the dummy gate dielectric 1022 that are disposed over the dummy fin structure 600B (i.e., the opening is centered on the gate structure being removed) [0061]: a mask 1403 may be formed over the dummy gate structures 1000 and 1020 to expose portions of the dummy gates 1004 and 1024 desired to be removed by forming openings 1405A in the I/O area 302A and 1405B (i.e., the mask openings are aligned with the gate structures that are to be etched). The motivation would be to ensure accurate gate-cut placement, maintain critical dimensions, prevent encroachment into neighboring gate structures, and to achieve intended isolation profiles as discussed in Jang where the openings are created specifically to cut the corresponding gate structures ([0058]-[0061], [0068]-[0070]) . 07-22-aia AIA Claim (s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 16 above, and further in view of U.S. Patent Application Publication No. 2023/0038762 (Chen ‘762) . Jang discloses 17. (Original) The method of claim 16, wherein forming the first isolation opening and the second isolation opening comprises: etching the first and second gate structures 1000 / 1020 to expose the fin structures 600A / 600B; etching through the fin structures 404A - 404B and into the substrate 302, wherein the first isolation opening 1500 extends into the substrate 302 for a first depth. Jang fails to disclose the second isolation opening extends into the substrate for a second depth, and the first depth is greater than the second depth. Chen ‘762 teaches A method comprising: wherein the first isolation opening 114D extends into the substrate 102 for a first depth, the second isolation opening 116D extends into the substrate 102 for a second depth, and the first depth is greater than the second depth (column y, lines 7-32). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first isolation opening at a greater depth than the second isolation opening in Jang. The motivation would be based on routine engineering process considerations such as varying the depth of the initial isolation trench depending upon the particular application as taught by Chen ‘762 (column 6, line 51 to column 7, line 6). See MPEP 2144.04. Jang discloses 18. (Currently Amended) The method of claim 17, wherein forming the plurality of gate structures 1000 / 1020 comprises forming a plurality of sacrificial gate structures ([0068]-[0075]), and further comprising: after depositing the dielectric layer 1702, performing a replacement gate process ([0076]-[0082]) . 07-22-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 16 above, and further in view of U.S. Patent Application Publication No. 2020/0266192 (Ju) . Jang fails to disclose 19. (Original) The method of claim 16, wherein the pattern further comprises: a third opening in align with a third gate structure of the plurality of gate structures, wherein the first gate structures and the third gate structure are immediately next to each other, the third opening has a third width along the first direction, and the first width is greater than the third width. Ju teaches A method comprising: wherein the pattern 113 further comprises: a third opening W13 in align with a third gate structure of the plurality of gate structures 107’, wherein the first gate structures and the third gate structure are immediately next to each other, the third opening W13 has a third width along the first direction, and the first width W11 is greater than the third width W13. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a third opening with a width less than the first width in Jang. The motivation would be based on routine engineering process considerations such as controlling the size of a device as taught by Ju ([0052]). See MPEP 2144.04 . 07-22-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang as applied to claim 16 above, and further in view of CN Publication No. 113270473 (Chen ‘473) . Jang fails to disclose 20. (Original) The method of claim 16, wherein the second opening comprises: a first segment; a second segment connected to the first segment; and a third segment connected to the second segment, wherein the first segment and the third segment are wider than the second segment. Chen ‘473 teaches A method comprising: wherein the opening 74 comprises: a first segment 74A; a second segment 74B connected to the first segment 74A; and a third segment 74C connected to the second segment 74B, wherein the first segment 74A and the third segment 74C are wider than the second segment 74B. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening having three segments in Jang. The motivation would be to improve lithographic process margin, reduce pattern collapse / merging, improve formation of the opening, help prevent or reduce leakage current and parasitic capacitance as discussed in Chen ‘473 . 07-21-aia AIA Claim (s) 21, 23-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Chen ‘762 . Jang discloses 21. (New) A method, comprising: forming a fin structure 404 on a semiconductor substrate 302, wherein the fin structure 404 extends along a first direction; forming a plurality of gate structures 1000 / 1020 across the fin structure 404 along a second direction; etching back the fin structure 404 to form a plurality of source/drain resources recesses (unlabeled) between the plurality of gate structures 1000 / 1020; forming a plurality of source/drain regions 1200 in the plurality of source/drain recesses (unlabeled); depositing a CESL ( contact etch stop layer ) (CESL) 1302 and an ILD ( interlayer dielectric ) ILD layer 1300 over the plurality of source/drain regions 1200; depositing a mask layer 1403 over the plurality of gate structures 1000 / 1020, the CESL 1302, and the ILD layer 1300; forming a pattern ([0061]) in the mask layer 1403, wherein the pattern comprises: a first mask opening 1405A in align with a first gate structure 1000 of the plurality of gate structures 1000 / 1020; and a second mask opening 1405B in align with the second gate structure 1020 of the plurality of gate structures 1000 / 1020, wherein the first gate structures 1000 and the second gate structure 1020 are immediately next to each other; forming a first isolation opening 1500 and a second isolation opening 1550 from the first mask opening 1405A and the second mask opening 1405B, wherein the isolation opening 1500 has a first depth; and depositing a dielectric layer 1702 to fill the first isolation opening 1500 and the second isolation opening 1550. Even assuming arguendo that Jang does not explicitly disclose a first opening in align with a first gate structure and a second opening in align with the second gate structure, wherein the first gate structures and the second gate structure are immediately next to each other, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to do so based on the language in the below paragraphs. [0058]: dummy gate structures 1000 and 1020 are respectively cut, intercepted, or otherwise disconnected to form a gate cut trench 1400 in the I/O area 302A and a gate cut trench 1450 in the core area 302B (i.e., the openings are formed by cutting the gate structures) [0059]: the gate cut trenches 1400 and 1450 is formed across a certain portion of each of the dummy gate structures 1000 and 1020 (i.e., the opening is located on / through the gate structure) [0060]: remove a portion of the dummy gate 1004 and a portion of the dummy gate dielectric 1002 that are disposed over the dummy fin structure 600A and remove a portion of the dummy gate 1024 and a portion of the dummy gate dielectric 1022 that are disposed over the dummy fin structure 600B (i.e., the opening is centered on the gate structure being removed) [0061]: a mask 1403 may be formed over the dummy gate structures 1000 and 1020 to expose portions of the dummy gates 1004 and 1024 desired to be removed by forming openings 1405A in the I/O area 302A and 1405B (i.e., the mask openings are aligned with the gate structures that are to be etched). The motivation would be to ensure accurate gate-cut placement, maintain critical dimensions, prevent encroachment into neighboring gate structures, and to achieve intended isolation profiles as discussed in Jang where the openings are created specifically to cut the corresponding gate structures ([0058]-[0061], [0068]-[0070]). Jang fails to disclose the second isolation opening has a second depth, and the first depth is greater than the second depth. Chen ‘762 teaches A method comprising: wherein the first isolation opening 114D extends into the substrate 102 for a first depth, the second isolation opening 116D extends into the substrate 102 for a second depth, and the first depth is greater than the second depth (column 7, lines 7-32). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first isolation opening at a greater depth than the second isolation opening in Jang. The motivation would be based on routine engineering process considerations such as varying the depth of the initial isolation trench depending upon the particular application as taught by Chen ‘762 (column 6, line 51 to column 7, line 6). See MPEP 2144.04. Jang discloses 23. (New) The method of claim 21, wherein the first mask opening 1405A has a first width along the first direction, the second mask opening 1405B has a second width along the first direction, and the first width is greater than the second width. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the optimum opening width relative to gate pitch in the modified method of Jang based on routine engineering considerations. The motivation would be to prevent optical diffraction overlap (such as proximity effects), mitigate pattern collapse in high-aspect-ratio features, and accommodate mask misalignment. This allows for the reliable formation of critical self-aligned features. See MPEP 2144.04. 24. (New) The method of claim 23, wherein the first width is greater than 0.5 times of the gate pitch. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the optimum isolation structure distance relative to gate pitch in the modified method of Jang based on routine engineering considerations. The motivation would be to prevent gate-to-gate shorting, reduce parasitic capacitance, and ensure sufficient space for lithography and spacer etching. See MPEP 2144.04. 25. (New) The method of claim 21, wherein the first isolation structure is a first distance away from the second isolation structure along the first direction, and the first distance is greater than 0.5 times of the gate pitch. Depending on engineering or design application, the choice between these a single channel or a multiple channel structure directly dictates performance (i.e., routine optimization). See MPEP See MPEP 2144.05. 26. (New) The method of claim 21, wherein the fin structure includes a single channel. Depending on engineering or design application, the choice between these a single channel or a multiple channel structure directly dictates performance (i.e., routine optimization). See MPEP See MPEP 2144.05. 27. (New) The method of claim 21, wherein the fin structure includes two or more channel layers . 07-22-aia AIA Claim (s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Chen ‘762 as applied to claim 21 above, and further in view of U.S. Patent Application Publication No. 2024/0395813 (Peng) . The combination of references fails to teach 22. (New) The method of claim 21, wherein the plurality of gate structures are evenly distributed along the first direction at a gate pitch. Peng teaches A method comprising: wherein the plurality of gate structures 40 are evenly distributed along the first direction at a gate pitch ([0057]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to evenly distributed gate structures in the modified device of Jang. The motivation would be scaling device density, and improving manufacturing uniformity as taught by Peng ([0012], [0023], [0053]) as well as maintaining electrostatic control . 07-22-aia AIA Claim (s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Chen ‘762 as applied to claim 23 above, and further in view of Ju . The combination of references fails to teach 28. (New) The method of claim 23, further comprising forming a third mask opening in the mask layer over a third gate structure of the plurality of gate structures, wherein the third gate structure is disposed immediately next to the first gate structure, and the third mask opening has a third width less than the first width. The combination of references fails to teach 29. (New) The method of claim 23, further comprising forming a third mask opening in the mask layer over a third gate structure of the plurality of gate structures, wherein the third gate structure is disposed immediately next to the first gate structure, and the third mask opening has a third width greater than the second width. Ju teaches A method comprising: forming a third mask opening W13 in the mask layer 113 over a third gate structure of the plurality of gate structures 107’, wherein the third gate structure is disposed immediately next to the first gate structure, and the third mask opening W13 has a third width less than the first width W11. These are just labels such that the third mask opening could be W11 to meet the requirement that one opening has a third width greater than the second width. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a third opening with a width less than the first width in the modified method of Jang. The motivation would be based on routine engineering process considerations such as controlling the size of a device as taught by Ju ([0052]). See MPEP 2144.04 . 07-21-aia AIA Claim (s) 30-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Chen ‘473 . Jang discloses 30. (New) A method, comprising: forming a plurality of fin structures 404A- 404D on a semiconductor substrate 302, wherein the fin structure 404 extends along a first direction; forming a gate structure 1000 / 1020 across the plurality of fin structures 404A- 404D along a second direction; etching back the plurality of fin structures 404A - 404D to form a plurality of source/drain resources recesses (unlabeled) on two sides of the gate structures 1000 / 1020; forming a plurality of source/drain regions 1200 in the plurality of source/drain recesses (unlabeled); depositing a CESL ( contact etch stop layer ) (CESL) 1302 and an ILD ( interlayer dielectric ) ILD layer 1300 over the plurality of source/drain regions 1200; depositing a mask layer 1403 over the plurality of gate structures 1000 / 1020, the CESL 1302, and the ILD layer 1300; forming a mask opening 1405A / 1405B in the mask layer 1403; forming an isolation opening 1500 / 1550 from the mask opening 1403; and depositing a dielectric layer 1702 to fill the solation opening 1500 / 1550 to form a gat isolation structure 1500 / 1550 in the gate structure 1000 / 1020, wherein the isolation structure 1500 / 1550. Jang fails to disclose wherein the isolation structure comprises: a first segment having a first width; and a second segment having a second width, wherein the first width is greater than the second width. Chen ‘473 teaches A method comprising: wherein the opening 74 comprises: a first segment 74A; a second segment 74B connected to the first segment 74A; and a third segment 74C connected to the second segment 74B, wherein the first segment 74A and the third segment 74C are wider than the second segment 74B. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening having three segments in Jang. The motivation would be to improve lithographic process margin, reduce pattern collapse / merging, improve formation of the opening, help prevent or reduce leakage current and parasitic capacitance as discussed in Chen ‘473. Chen ‘473 teaches 31. (New) The method of claim 30, wherein the first segment 74A cuts into a first fin structure of the plurality of fin structures 24, and the second segment 74B cuts into a second fin structure of the plurality of fin structures 24. Chen ‘473 teaches 32. (New) The method of claim 31, wherein the first segment 74A is connected to the second segment 74B. Chen ‘473 teaches 33. (New) The method of claim 32, wherein the first segment 74A extends into the semiconductor substrate 20 for a first depth, the second segment 74B extends into the semiconductor substrate 20 for a second depth, and the first depth is greater than the second depth (D1 - D3). Jang discloses 34. (New) The method of claim 31, further comprising: forming a second gate structure 1020 disposed next to the gate structure 1000; and forming a second isolation structure 1550 disposed in the second gate structure 1020, wherein the second isolation structure 1550 cuts into the second fin structure 1020, the second isolation structure has a third width, and the third width is greater than the second width. Chen 473’ teaches 35. (New) The method of claim 34, wherein the isolation structure 22 further comprises: a third segment 74C cutting into a third fin structure of the plurality of fin structures 24, wherein the third segment 74C and the first segment 74A are connected to two ends of the second segment 74B, the third segment 74C has a fourth width, and the fourth width is greater than the second width. This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Nos. 9,455,198 (Yu), 11,251,284 (Lin), U.S. Patent Application Publication No. 2022/0384659 (Stamper) teach a method for manufacturing of a semiconductor substrate . Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/Primary Examiner, Art Unit 2893 Application/Control Number: 18/421,312 Page 2 Art Unit: 2893 Application/Control Number: 18/421,312 Page 3 Art Unit: 2893 Application/Control Number: 18/421,312 Page 4 Art Unit: 2893 Application/Control Number: 18/421,312 Page 5 Art Unit: 2893 Application/Control Number: 18/421,312 Page 6 Art Unit: 2893 Application/Control Number: 18/421,312 Page 7 Art Unit: 2893 Application/Control Number: 18/421,312 Page 8 Art Unit: 2893 Application/Control Number: 18/421,312 Page 9 Art Unit: 2893 Application/Control Number: 18/421,312 Page 10 Art Unit: 2893 Application/Control Number: 18/421,312 Page 11 Art Unit: 2893 Application/Control Number: 18/421,312 Page 12 Art Unit: 2893 Application/Control Number: 18/421,312 Page 13 Art Unit: 2893 Application/Control Number: 18/421,312 Page 14 Art Unit: 2893 Application/Control Number: 18/421,312 Page 15 Art Unit: 2893 Application/Control Number: 18/421,312 Page 16 Art Unit: 2893 Application/Control Number: 18/421,312 Page 17 Art Unit: 2893 Application/Control Number: 18/421,312 Page 18 Art Unit: 2893 Application/Control Number: 18/421,312 Page 19 Art Unit: 2893 Application/Control Number: 18/421,312 Page 20 Art Unit: 2893
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