DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1, and Subspecies 7 in the reply filed on 1 May 2026 is acknowledged. Applicant’s election without traverse of Species 1 in the reply filed on 25 August 2026 is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Subspecies 7 (Figure 4G does not show a constant duty ratio of an array of patterns as claimed in claim 8), there being no allowable generic or linking claim. Election was made without traverse in the replies filed on 1 May 2026 and 25 August 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-10, and 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (“Kim” US 2019/0155174).
Regarding claim 1, Kim discloses a semiconductor device (Figure 11), comprising:
a substrate (10) including a plurality of chip regions (one chip region is the region including the top row of three regions CA plus the first CA of the second row in Figure 11, another chip region is the region including the lowest row of three regions CA plus the third CA of the second row in Figure 11, see annotated Figure 11 below);
a plurality of scribe lines (SL) interposing the plurality of chip regions (see Figure 11);
a first plurality of alignment mark regions (100, the plurality within scribe lines SL) distributed within the plurality of scribe lines (SL, see Figure 11); and
a second plurality of alignment mark regions (100, within CA’s) distributed within each of the plurality of chip regions (see Figure 11 and annotated Figure 11).
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Regarding claim 2, Kim discloses wherein the first plurality of alignment mark regions (100 within SL) are located both at one or more exposure field corners (far corners of the substrate, see Figure 11) and between adjacent chip regions of the plurality of chip regions (see Figure 11, mark region 100 within SL’s are also between the regions labeled in annotated Figure 11).
Regarding claim 3, Kim discloses wherein the second plurality of alignment mark regions (marks 100 within CA’s) are uniformly distributed throughout an area (CA) of each chip region of the plurality of chip regions (see annotated Figure 11).
Regarding claim 4, Kim discloses wherein the second plurality of alignment mark regions (marks 100 within CA’s) includes at least one alignment mark region (100) within each quadrant (CA) of each chip region (labeled in annotated Figure 11) of the plurality of chip regions (see annotated Figure 11, where quadrant is interpreted to mean four, evenly divided parts CA of the chip regions labeled in annotated Figure 11).
Regarding claim 5, Kim discloses wherein each of the first and second plurality of alignment mark regions (100) include a cell (100, Figure 3B) having a pattern (110/120) that defines an alignment mark (see Figure 3B).
Regarding claim 6, Kim discloses wherein a dummy pattern (31) is disposed adjacent to the cell (100) within each of the first and second plurality of alignment mark regions (100, see Figure 3B).
Regarding claim 7, Kim discloses wherein the pattern (110/120) includes an array of patterns having a first duty ratio along a first direction (y-direction in the Figures) in a first region (110) of the pattern (110/120) and a second duty ratio along the first direction (y-direction) in a second region (120) of the pattern (110/120, each individual patterns 110 and 120 of the pattern 110/120 have different duty ratios at least because of the different spacing between the sub-patterns of each pattern and the widths of each sub-pattern).
Regarding claim 9, Kim discloses wherein the pattern (110/120) includes an array of patterns having a varying duty ratio (see Figure 3B, the spacings between sub-patterns 122 and 110x are different), and wherein the varying duty ratio is provided by at least one of a varying width of individual patterns (122/110x) of the array of patterns (110/120) and a varying spacing of adjacent patterns of the array of patterns (see Figure 3B, the widths and the spacings are different with each individual pattern).
Regarding claim 10, Kim discloses wherein the pattern (110/120) includes an array of patterns having a first duty ratio (duty ratio of sub-patterns 110x) along a first direction (y-direction in the Figures, see Figure 3B) and a second duty ratio (duty ratio of sub-patterns 122) along a second direction (x-direction) different than the first direction (y-direction and x-direction are different, labeled in the Figures of Kim).
Regarding claim 21, Kim discloses a semiconductor device (Figure 11), comprising:
a substrate (10) having a first chip region and a second chip region adjacent to the first chip region (the first chip region is the region including the top row of three regions CA plus the first CA of the second row in Figure 11, the second chip region is the region including the lowest row of three regions CA plus the third CA of the second row in Figure 11, see annotated Figure 11 below); and
scribe lines (SL) surrounding the first and second chip regions (see Figure 11);
wherein the scribe lines (SL) include plural alignment mark regions (100, in SL regions of Figure 11) distributed at regular intervals along the scribe lines (SL, see Figure 11); and
wherein two or more alignment mark regions (100 in CA’s in Figure 11) are disposed within each quadrant of each of the first chip region and the second chip region (see annotated Figure 11, where quadrant is interpreted to mean four, evenly divided parts CA of the chip regions labeled in annotated Figure 11).
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Regarding claim 22, Kim discloses wherein the plural alignment mark regions (100 in SL) are disposed at one or more exposure field corners the first and second chip regions (outer corners of the substrate in Figure 11).
Regarding claim 23, Kim discloses wherein the plural alignment mark regions (100 in SL) are disposed between the first and second chip regions (see annotated Figure 11).
Regarding claim 24, Kim discloses wherein the two or more alignment mark regions (100 in chip regions) are uniformly distributed throughout each quadrant (CA quadrants) of each of the first chip region and the second chip region (see annotated Figure 11, where quadrant is interpreted to mean four, evenly divided parts CA of each chip regions labeled in annotated Figure 11).
Regarding claim 25, Kim discloses wherein the plural alignment mark regions (100 in SL) and the two or more alignment mark regions (100 in chip regions) each include a cell (FR, see Figure 3B) having a pattern that defines an alignment mark (see patterns in Figure 3B), and wherein a plurality of dummy patterns (31) are disposed adjacent to two or more sides of the cell (FR, see Figure 3B).
Regarding claim 26, Kim discloses wherein each of the plurality of dummy patterns (31) includes an array of rectangular features, square features, circular features, line features, or a combination thereof (see Figure 3B, shows square shape).
Regarding claim 27, Kim discloses wherein each of the plurality of dummy patterns (31) are spaced a distance from respective ones of the two or more sides of the cell (FR, see Figure 3B), and wherein the distance is equal to or greater than 1 micron (G1 is approximately 2 microns, see para. [0028], Figure 3B, thus the spacing between he cell FR and the dummy patterns 31 is at least 1 micron).
Regarding claim 28, Kim discloses a semiconductor device (Figure 11), comprising:
a substrate (10) including a first patterned layer (lower layer, para. [0040]) and a second patterned layer (upper layer, para. [0040]) over the first patterned layer (see para. [0040]);
a plurality of chip regions (CA), wherein each of the plurality of chip regions (CA) includes the first and second patterned layers (see Figure 3B, para. [0040]);
a plurality of scribe lines (SL) interposing the plurality of chip regions (CA, see Figure 11);
a first number of alignment mark regions (122d) disposed within the first patterned layer (lower layer) of each of the plurality of chip regions (see para. [0040], Figures 3B, 11); and
a second number of alignment mark regions (122u/110) disposed within the second patterned layer (upper layer, para. [0040], see Figure 3B) of each of the plurality of chip regions (see Figures 3B, 11);
wherein the first number of alignment mark regions is different than the second number of alignment mark regions (the number of regions of patterns 122d is less than that of patterns 122u/110, see Figure 3B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 5 and 28 above, respectively, and further in view of Han et al. (“Han” US 2024/0153883).
Regarding claim 11, Kim does not explicitly teach the duty ratio values.
Han teaches an alignment pattern (100/200/500 in OTS region, see Figure 1) wherein the pattern includes an array of patterns (100/200/500) having a duty ratio in a range from about 0.5 to about 3 (see duty ratio w1/p1 and w2/p2 of patterns 100 and 200, respectively, in Figure 2A, para. [0055] discloses w1/p1 and w2/p2, where w1 and w2 are 100nm to 300nm, and p1 and p2 are 300nm to 600nm, thus overlaps with the claimed range, and the duty ratio w3/p3 of pattern 500, where w3 is equal to w1 and w2, 100/300nm and p3 is 350nm, see para. [0059], overlaps with the claimed range as well).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Han above into the teachings of Kim to include the duty ratio range as claimed for the purpose of improving precision of alignment (Han, para. [0111]).
Regarding claim 29, Kim does not explicitly teach semiconductor device features defined by the patterned layers.
Han teaches wherein each of the first and second patterned layers (100/200/500, alignment keys AK1/NL/AK2) define different semiconductor device features, and wherein the semiconductor device features include source/drain contacts, source/drain vias, gate vias, backside vias, interconnect lines, or gate stack features (see Figure 15, the alignment keys/overlay targets define/determine bonding of different device layers, or interconnects, shown in Figure 15).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Han above into the teachings of Kim to include the alignment first and second patterns to define semiconductor device features in order to precisely measure alignment errors in manufacture (Han, para. [0111]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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