DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Applicant’s amendment to the claims, filed on December 8th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
2. Applicant’s arguments/remarks, see pgs. 6-8, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks directed towards the newly amended limitations of at least the independent claims:
The Examiner notes that a new combination of prior art are utilized such that arguments directed solely to the previously presented combination are now moot.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Objections
4. Claims 10-17 are objected to because of the following informalities:
Claim 10 recites in the second to last line “wherein filling-metal region” which should be changed to “wherein the filling-metal region” for proper antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 8-15, 18-20, 22-23 are rejected under 35 U.S.C. 103 as obvious over Lim et al. (US 2018/0175165 A1), hereinafter as Lim, in view of Ramachandran et al. (US 2012/0175711 A1), hereinafter as R1
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6. Regarding Claim 1, Lim discloses a structure (see Figs. 1-15B, “1st Labeled Fig. 15B” above, embodiment of Fig. 15B for which the only difference is a height of the elements described in [0043]) comprising:
a first gate stack (elements 154, 156, 162, 162A-C, 166, see [0028-0029 & 0036]) comprising:
a first high-k dielectric layer (element 156, see [0028] “High-k dielectric layers 156 and 256”);
a first work-function layer (element 162B, see [0031] Selected as TiN) overlapping a bottom portion of the first high-k dielectric layer;
a first blocking layer (element 162C, see [0031] “162A/262A, 162B/262B, and 162C/262C may include a TiN layer, a TaN layer, and another TiN layer” Selected as TiN;
Note, though the material of the blocking layer is not claimed, the same material is provided in Applicant’s specification see [0030-0031 & 0033]) overlapping a bottom portion of the first work-function layer; and
a first metal layer (element 166, see [0036] “the filling metal is homogenous, which may be formed of W, Cu, Co. Al, Ru, etc. or alloys thereof, providing the filling material has a low resistivity”) overlapping and contacting the first work-function layer and the first blocking layer (see Fig. 15B), wherein the first block layer and the first metal layer form an interface (see Fig. 15B), and the interface extends from a vertical center line of the first gate stack in opposing lateral directions (see Fig. 15B); and
a second gate stack (element 254, 256, 262, 262A-C, 266, see [0028-0029 & 0036]) comprising:
a second high-k dielectric layer (element 256, see [0028] “High-k dielectric layers 156 and 256”);
a second work-function layer (element 262A, see [0031] Selected as TiN) overlapping a bottom portion of the second high-k dielectric layer (see Fig. 15B);
a second blocking layer (element 262B, see [0028] selected as TiAlN;
Note, though the material of the blocking layer is not claimed, the same material is provided in Applicant’s specification see [0030-0031 & 0033]) overlapping a bottom portion of the second work-function layer, wherein the first blocking layer and the second blocking layer comprise a same metal compound (see [0028]);
a metal filling layer (labeled element “Metal Filling Layer”, lower layer of element 266, see [0036]) over the second blocking layer (see “1st Labeled Fig. 15B”); and
a second metal layer (labeled element “Second Metal Layer”, upper layer of element 266, see [0036]) overlapping and contacting the second work-function layer and the second blocking layer (see “1st Labeled Fig. 15B”).
Lim does not disclose wherein the metal filling layer and the second metal layer comprise different materials.
R1 discloses wherein the metal filling layer and the second metal layer comprise different materials (see in particular Fig. 18 the metal filling layer element 46 and the second metal layer element 60 are different material, see [0084] “metal layer 46 can be composed of an elemental metal such as Al, Au, Ag, Cu, or W or an alloy thereof” and [0093] “The another contact metal 60 may comprise the same or different, typically, the same conductive metal as that of the contact metal 34” and [0071] “The contact metal 34 that can be employed in the present application includes any conductive metal-containing material including, for example, W, Al, Cu, and alloy thereof” Selected to be different)
The material relationship of the metal filling layer and the second metal layer as taught by R1 is incorporated as a material relationship of the metal filling layer and the second metal layer of Lim.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of R1 with Lim because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material relationship of the metal filling layer and the second metal layer for another in a similar device for which the two options are provided as alternatives to obtain predictable results (see R1 [0093]).
7. Regarding Claim 2, Lim,R1 disclose the structure of claim 1 further comprising a dielectric filling region over (Fig. 15B region of element 172 and inner portion of element 78, see [0040] “Hard masks 172 and 272 may be dielectric hard masks” [0042] “etch stop layer 78”) and contacting the first metal layer and the first high-k dielectric layer (see Fig. 15B).
8. Regarding Claim 3, the structure of claim 2 further comprising a gate spacer (element 138, see [0028] “gate spacers 138 and 238”) contacting a sidewall of the first high-k dielectric layer, wherein the dielectric filling region comprises a high portion (inner portion of element 78) overlapping the gate spacer (see Fig. 15B high portion of element 78 overlapping element 138).
9. Regarding Claim 5, Lim,R1 disclose the structure of claim 3 further comprising a contact etch stop layer (element 80 and outer portion of element 78, see [0042] “Etch stop layer 78 … ILD 80”; note, claim as currently recited does not recite a material limitation and any ILD can also function as a contact etch stop layer to a tailored etch) contacting the gate spacer (see Fig. 15B), wherein the contact etch stop layer comprises a part higher than the a top edge of the gate spacer (see Fig. 15B).
10. Regarding Claim 8, Lim,R1 disclose the structure of claim 1, wherein the first metal layer is lower than a top edge of the first high-k dielectric layer (see Fig. 15B).
11. Regarding Claim 9, Lim,R1 disclose the structure of claim 1, wherein the second gate stack is wider than the first gate stack (see Fig. 15B and [0024]).
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12. Regarding Claim 10, Lim discloses a structure (see Figs. 1-15B, “2nd Labeled Fig. 15B” above, embodiment of Fig. 15B for which the only difference is a height of the elements described in [0043]) comprising:
a first gate stack (elements 154, 156, 162, 162A-C, 166, see [0028-0029 & 0036]) comprising:
a first gate dielectric (element 156, see [0028] “High-k dielectric layers 156 and 256”); and
a first gate electrode comprising:
a first work-function layer (element 162B, see [0031] Selected as TiN) over the first gate dielectric;
a first blocking layer (element 162C, see [0031] Selected as TiAlN;
Note, though the material of the blocking layer is not claimed, the same material is provided in Applicant’s specification see [0030-0031 & 0033]) comprising titanium nitride over and contacting the first work-function layer (see Fig. 15B);
a first metal layer (element 166, see [0036] “the filling metal is homogenous, which may be formed of W, Cu, Co. Al, Ru, etc. or alloys thereof, providing the filling material has a low resistivity”) over and contacting the first work-function layer and the first blocking layer (see Fig. 15B), wherein an entire top surface of the first blocking layer is in contact with the first metal layer (see Fig. 15B); and
a second gate stack (element 254, 256, 262, 262A-C, 266, see [0028-0029 & 0036]) wider than the first gate stack (see Fig. 15B and [0024]), the second gate stack comprising:
a second gate dielectric (element 256, see [0028] “High-k dielectric layers 156 and 256”); and
a second gate electrode comprising:
a second work-function layer (element 262A, see [0031] “162A/262A, 162B/262B, and 162C/262C may include a TiN layer, a TaN layer, and another TiN layer, respectively” TiN) over the second gate dielectric (see Fig. 15B);
a second blocking layer (element 262B-C, see [0028] comprises TiN element 262C;
Note, though the material of the blocking layer is not claimed, the same material is provided in Applicant’s specification see [0030-0031 & 0033]) comprising titanium nitride over and contacting the second work-function layer (see Fig. 15B);
a filling-metal region (portion of element 266 below a top surface of element 262C, see [0036]) over the first blocking layer; and
a second metal layer (portion of element 266 above a top surface of element 262C; note, the manner in which the claim is currently recited does not provide a difference in material between the filling-metal region and the second metal layer such as to distinguish from the prior art), wherein top surfaces (central top surface and peripheral top surfaces) of the second blocking layer are in physical contact with both a first bottom surface of the filling-metal region (central top surface of element 262C in physical contact with a first bottom surface of the “Filling-Metal Region”) and a second bottom surface of the second metal layer (peripheral top surfaces in contact with a second bottom surface of the ”Second Metal Layer”).
Lim does not disclose wherein filling-metal region and the second metal layer form a distinguishable interface in between.
R1 discloses wherein filling-metal region and the second metal layer form a distinguishable interface in between (see in particular Fig. 18 the metal filling layer element 46 and the second metal layer element 60 are different material, see [0084] “metal layer 46 can be composed of an elemental metal such as Al, Au, Ag, Cu, or W or an alloy thereof” and [0093] “The another contact metal 60 may comprise the same or different, typically, the same conductive metal as that of the contact metal 34” and [0071] “The contact metal 34 that can be employed in the present application includes any conductive metal-containing material including, for example, W, Al, Cu, and alloy thereof” Selected to be different)
The material relationship of the metal filling layer and the second metal layer as taught by R1 is incorporated as a material relationship of the metal filling layer and the second metal layer of Lim.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of R1 with Lim because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material relationship of the metal filling layer and the second metal layer for another in a similar device for which the two options are provided as alternatives to obtain predictable results (see R1 [0093]).
13. Regarding Claim 11, Lim,R1 disclose the structure of claim 10, wherein the first gate electrode comprises fewer layers than the second gate electrode (see Fig. 15B the second gate electrode comprises an additional element when counting the portions of element 266 as separate).
14. Regarding Claim 12, Lim,R1 disclose the structure of claim 10, wherein the first metal layer and the second metal layer comprise a same metal as the filling-metal region (see “2nd Labeled Fig. 15B” above, the three elements are a same material of elements 166,266, see [0036]).
15. Regarding Claim 13, Lim,R1 disclose the structure of claim 10, wherein the first metal layer and the second metal layer comprise a metal selected from the group consisting of molybdenum, tungsten (see [0036]), cobalt, and combinations thereof.
16. Regarding Claim 14, Lim,R1 disclose the structure of claim 10, wherein the first metal layer is lower than a top end of the first gate dielectric (see Fig. 15B).
17. Regarding Claim 15, Lim,R1 disclose the structure of claim 10 further comprising a gate spacer (element 138, see [0028] “gate spacers 138 and 238”) contacting the first gate stack, wherein the first metal layer is lower than a top end of the gate spacer (see Fig. 15B).
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18. Regarding Claim 18, Lim discloses a structure (see Figs. 1-15B, “3rd Labeled Fig. 15B” above, embodiment of Fig. 15B for which the only difference is a height of the elements described in [0043]) comprising:
a gate spacer (element 238, see [0039] “gate spacers 138 and 238”);
a gate stack (elements 254, 256, 262, 262A-C, 266, see [0028-0029 & 0036]) comprising:
a gate dielectric (element 256, see [0028] “High-k dielectric layers 156 and 256”);
a plurality of conductive layers (elements 262 and labeled “Filling-Metal Layer”, see [0029] “metal-containing conductive layers 162 and 262 are formed through deposition” and [0036] “metal layers 166 and 266”) on the gate dielectric, wherein the plurality of conductive layers comprise a lower layer (element TiN layer of the stack, see [0031] “162A/262A, 162B/262B, and 162C/262C may include a TiN layer, a TaN layer, and another TiN layer, respectively) and a topmost layer (labeled element “Topmost Layer” which is a lower portion of metal layer element 266, see [0036]) over the lower layer (see “3rd Labeled Fig. 15B” above), and the topmost layer has a lower resistivity than the lower layer (TiN has a material property with a lower resistivity than the material property of the metal);
a metal layer (labeled element “Metal Layer”, see [0036]) over and contacting top surfaces of the plurality of conductive layers (see “3rd Labeled Fig. 15B” above),
wherein a first sidewall of the metal layer contacts a second sidewall of the gate dielectric (see “3rd Labeled Fig. 15B” above);
a dielectric filling region (Fig. 15B region of element 272 and inner portion of element 78, see [0040] “Hard masks 172 and 272 may be dielectric hard masks” [0042] “etch stop layer 78”) comprising:
a first portion over (inner portion of element 78 and element 272) and contacting the gate spacer (see Fig. 15B), wherein a part of the first portion is lower than a first top end of the gate spacer (element 272 portion is lower than a top surface of element 238); and a second portion (lower portion of element 272 directly contacting element 266) over and contacting the metal layer (see “3rd Labeled Fig. 15B” above); and
a source/drain region (elements 242, see [0025] “source/drain regions 142 and 242”) aside the gate spacer.
Lim does not disclose wherein the metal layer and the topmost layer comprise different materials.
R1 discloses wherein the metal layer and the topmost layer comprise different materials (see in particular Fig. 18 the metal filling layer element 46 and the second metal layer element 60 are different material, see [0084] “metal layer 46 can be composed of an elemental metal such as Al, Au, Ag, Cu, or W or an alloy thereof” and [0093] “The another contact metal 60 may comprise the same or different, typically, the same conductive metal as that of the contact metal 34” and [0071] “The contact metal 34 that can be employed in the present application includes any conductive metal-containing material including, for example, W, Al, Cu, and alloy thereof” Selected to be different)
The material relationship of the metal filling layer and the second metal layer as taught by R1 is incorporated as a material relationship of the metal filling layer and the second metal layer of Lim.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of R1 with Lim because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material relationship of the metal filling layer and the second metal layer for another in a similar device for which the two options are provided as alternatives to obtain predictable results (see R1 [0093]).
19. Regarding Claim 19, Lim,R1 disclose the structure of claim 18 further comprising a contact etch stop layer (element 80 and outer portion of element 78, see [0042] “Etch stop layer 78 … ILD 80”; note, claim as currently recited does not recite a material limitation and any ILD can also function as a contact etch stop layer to a tailored etch) comprising:
a first part overlapping the source/drain region (first part over element 242); and
a second part contacting the gate spacer (second part contacting element 238), wherein the second part comprises a second top end higher than the first top end of the gate spacer (see Fig. 15B).
20. Regarding Claim 20, Lim,R1 disclose the structure of claim 19, wherein the second part of the contact etch stop layer further contacts the dielectric filling region (see Fig. 15B).
21. Regarding Claim 22, Lim,R1 disclose the structure of claim 1, wherein in a cross-section of the structure, the metal filling layer has a rectangular cross-sectional shape (see “1st Labeled Fig. 15B” above)
22. Regarding Claim 23, Lim,R1 disclose the structure of claim 18, wherein the metal layer and the topmost layer comprise a same metal (see “2nd Labeled Fig. 15B” above, the two elements are a same material of elements 166,266, see [0036])
23. Claims 16-17 are rejected under 35 U.S.C. 103 as obvious over Lim et al. (US 2018/0175165 A1), hereinafter as Lim, in view of Ramachandran et al. (US 2012/0175711 A1), hereinafter as R1, in view of Ho et al. (US 2016/0056262 A1), hereinafter as Ho
24. Regarding Claim 16, Lim,R1 disclose the structure of claim 15 further comprising:
a source/drain region (elements 142, see [0025] “source/drain regions 142 and 242”) on a side of the first gate dielectric.
Lim,R1 do not disclose a contact etch stop layer comprising a first portion over and contacting the source/drain region, and a second portion contacting the gate spacer.
Ho discloses (see Fig. 1) discloses a contact etch stop layer (element 205, see [0017] “contact etch stop layer 205”) comprising a first portion over and contacting the source/drain region (elements 206, see [0013] “The doped region 206 may be an epitaxial layer on each side of metal gate 211. The epitaxial layer may be a raised source and drain regions.”) (see Fig. 1), and a second portion contacting the gate spacer (second left sidewall of a first gate spacer left element 204, see [0010] “sidewall spacer 204”) (see Fig. 1).
The contact etch stop layer as taught by Ho is incorporated as a contact etch stop layer of Lim.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Ho with Lim because the combination allows better control of an etching profile for formation of the source and drain contact and for the gate structure, allows use of one or more etching processes with different etchants for different compositions of materials, and allows better control and adjustability of the ultimate structure of the source and drain contact regions and gate structure effecting the electrical connection and operation of the transistor (see Ho [0038, 0040]).
25. Regarding Claim 17, Lim,R1,Ho disclose the structure of claim 16, further comprising a dielectric filling region (Fig. 15B region of element 172 and inner portion of element 78, see [0040] “Hard masks 172 and 272 may be dielectric hard masks” [0042] “etch stop layer 78”) comprising a portion overlapping the first metal layer (see Lim Fig. 15B), wherein the second portion of the contact etch stop layer further contacts the dielectric filling region (see Fig. 15B).
26. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2018/0175165 A1), hereinafter as Lim, in view of Ramachandran et al. (US 2012/0175711 A1), hereinafter as R1, in view of Tseng et al. (US 2015/0270177 A1), hereinafter as Tseng
27. Regarding Claim 21, Lim,R1 disclose the structure of claim 1.
Lim,R1 do not disclose wherein the first gate stack has a first total count of layers, and the second gate stack has a second total count of layers different from the first total count of layers
Tseng discloses wherein the first gate stack has a first total count of layers (see Fig. 9 first stack of element 52 has a first total count of five layers), and the second gate stack has a second total count of layers different from the first total count of layers (see Fig. 9 second stack of element 53 has a second total count of six layers – extra work function layer).
The second gate stack having an extra work function layer compared to the first gate stack as taught by Tseng is incorporated as the second gate stack having an extra work function layer compared to the first gate stack of Lim.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Tseng with Lim because the combination allows for work function adjustment tailored to each respective gate, and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of work function layers of two gate structures in a similar device for another to obtain predictable results (see Tseng Fig. 9 and see Lim [0031] “Layers 162 and 262 may also include two layers or more than three layers” the number of work function layers is selectable).
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818