DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species ‘a’ in the reply filed is acknowledged. Based on the art now of record, the Examiner has determined the requirement unnecessary and is therefore withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hidaka (US 2003/0156448).
Regarding claim 16, Hidaka discloses a method, comprising: generating, by a first local word line driver (see Figure 2, RSD21 for example), a first word line voltage on a word line to access a first memory cell in a first memory array of a first memory bank in a first operation (see Figure 3, read operation), wherein the first local word line driver is arranged in a control region of the first memory bank; and generating, by a global word line driver (30), a second word line voltage (for write operation) on the word line to access the first memory cell in the first memory array of the first memory bank in a second operation, wherein the global word line driver is arranged at an edge of a second memory bank (AR1) different from the first memory bank.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 11-13, 15 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hidaka in view of Chung (US 2010/0157664).
Regarding claim 1, Hidaka discloses a memory device, comprising: a plurality of first memory arrays (AR1, AR2); a plurality of first read word line drivers (RSD11, RSD12, etc.) each coupled to one array in the plurality of first memory arrays, wherein a selected one in the plurality of first read word line drivers is configured to generate a first word line voltage to a corresponding array in the plurality of first memory arrays in a first read operation (see Figure 3); and a first write word line driver (30) coupled to at least two drivers in the plurality of first read word line drivers, and configured to generate a second word line voltage (see Figure 3) to the plurality of first memory arrays in a first write operation.
Hidaka fails to teach that the second word line voltage is greater than the first word line voltage. However, as Chung teaches (see claim 10), it was known at the time of filing to provide read voltages on word lines of lower values in magnetoresistive memories. Therefore, it would have been obvious to one having ordinary skill at the time of filing to modify Hidaka to include features of the Chung reading wherein the read voltage applied on the word line would be lower than the program voltage since this was a know operational technique and yields the predictable result of a read memory cell.
Regarding claim 2, Hidaka discloses the memory device of claim 1, wherein the plurality of first read word line drivers are arranged in a plurality of first control regions of a plurality of memory banks, and the first write word line driver is arranged an edge of one in the plurality of memory banks (see Figure 2).
Regarding claim 3, Hidaka discloses the memory device of claim 2, wherein the first write word line driver is arranged between two of the plurality of memory banks (RSD21 is between AR1 and AR2).
Regarding claim 11, Hidaka discloses a memory device, comprising: a first word line extending in a first direction; a plurality of first read word line drivers (RSD21, RSD22, etc.) arranged in a plurality of first control regions that extend in a second direction (column) and are interposed between a plurality of first memory arrays (AR1, AR2), wherein a selected one in the plurality of first read word line drivers is configured to generate a first word line voltage to activate the first word line in a read operation; and a first write word line driver coupled to the first word line and configured to generate a second word line voltage to activate the first word line in a write operation, wherein the first word line voltage and the second word line voltage are different from each other (see rejection of claim 1 above).
Claim 4 and 15 recites substantially similar features as claim 1 (and 11) above but for an additional memory. Hidaka fails to teach this additional, duplicate memory. However, it would have been obvious to one having ordinary skill at the time of filing to duplicate the memory of Hidaka in order to increase the memory capacity and since it has been held that a duplication of parts requires only routine skill in the art.
Regarding claim 12, Hidaka discloses the memory device of claim 11, wherein the plurality of the first control regions are included in a plurality of memory banks, wherein the first word line crosses the plurality of memory banks (WWL’s cross multiple banks).
Regarding claim 13, Hidaka discloses the memory device of claim 12, wherein the first write word line driver is arranged at an edge of one in the plurality of memory banks (see Figure 2, 30).
Regarding claim 17, Hidaka discloses the method of claim 16, further comprising: generating, by a second local word line driver (RSD23 for example), the first word line voltage on the word line to access a second memory cell in a second memory array of the first memory bank in a third operation, wherein the second local word line driver is arranged in the control region of the first memory bank and coupled to the global word line driver through the word line, wherein the first word line voltage is smaller than the second word line voltage (see rejection of claim 1 above).
Regarding claim 18, Hidaka discloses the method of claim 17, further comprising: generating, by a third local word line driver, the first word line voltage on the word line to access a third memory cell in a first memory array of the second memory bank in a fourth operation, wherein the third local word line driver is arranged in a control region of the second memory bank and coupled to the global word line driver through the word line (this describes the operation on a cell in another sub array and is met by the same teachings as claims 16 and 17 above).
Allowable Subject Matter
Claims 5-10, 14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5-6, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a pass gate coupled between output terminals of the at least two drivers in the plurality of first read word line drivers, and configured to electrically connect a first portion of a word line with a second portion of the word line in the first write operation, wherein the first portion of the word line is coupled to a first driver in the at least two drivers, and the second portion of the word line is coupled to a second driver in the at least two drivers, wherein the first write word line driver is coupled to the plurality of first memory arrays through the word line.
Regarding claims 7-8, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a pass gate coupled between one in the plurality of first read word line drivers and one in the plurality of second read word line drivers; wherein the first write word line driver is further configured to generate the second word line voltage to the plurality of second memory arrays in a second write operation.
Regarding claim 9, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a plurality of pass gates each coupled between two adjacent first read word line drivers and configured to be turned on to electrically transmit the second word line voltage to the plurality of first memory arrays.
Regarding claim 10, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a plurality of pass gates each coupled between two adjacent first read word line drivers in the plurality of first read word line drivers, wherein a first group of the plurality of pass gates are configured to be turned on in response to a plurality of control signals to transmit the second word line voltage to some of the plurality of first memory arrays when a second group of the plurality of pass gates are turned off.
Regarding claim 14, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations wherein the memory device further comprises: a plurality of pass gates configured to electrically couple the plurality of portions of the first word line with each other in response to a plurality of control signals.
Regarding claim 19, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including transmitting, by first and second pass gates, the second word line voltage to the word line in response to a plurality of control signals, wherein the first pass gate is arranged in the control region of the first memory bank and coupled between output terminals of the first local word line driver and the second local word line driver, wherein the second pass gate is arranged between the first memory bank and the second memory bank and coupled between the second local word line driver and the third local word line driver.
Regarding claim 20, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including turning on a plurality of first pass gates to transmit the second word line voltage from the global word line driver to the first memory bank in the second operation while turning off a plurality of second pass gates to electrically disconnect a second memory bank from the global word line driver.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of hierarchical word line structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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