DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites in the last line “wherein the semiconductor channel is continuous.” Claim 15 recites “a continuous semiconductor layer overlying the first source/drain region and underlying the second source/drain region.” The specification does not provide support for a continuous semiconductor layer. The drawing actually show that the semiconductor layer is a discreet layer that repeats vertically (along the z axis). Furthermore, the lack of support in the specification makes it difficult to understand how the semiconductor layer is continuous. Is the semiconductor layer continuous along the vertical direction and being a single vertical layer that crosses thru or along adjacent memory cells. The limitations in question will be ignored until the applicant provides clarification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites in the last line “wherein the semiconductor channel is continuous.” Claim 15 recites “a continuous semiconductor layer overlying the first source/drain region and underlying the second source/drain region.” It is not how the semiconductor layer is continuous. There is no reference point from which to compare the structure of the layer. One cannot ascertain if the semiconductor is continuous between the conductive lines or if the semiconductor is continuous throughout the height/length of the device along the sidewalls of other cells. The limitations in question will be ignored until the applicant provides clarification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7, as far as understood, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rajashekhar et al. (US Pub. 2021/0242241 A1).
In re claim 1, Rajashekhar shows (fig. 5H) a memory device, comprising: a first conductive line (42S) and a second conductive line (42D) overlying the first conductive line, wherein the first and second conductive lines are elongated in a first direction; a first internal gate electrode (54) and a semiconductor channel (60) that overlie the first conductive line and that underlies the second conductive line; a first control gate (66 left) electrode and a second control gate electrode (66 right) that are arranged in a line extending in the first direction and that are on an opposite side of the first internal gate electrode as the semiconductor channel; and an insulator layer (52) separating the first control gate electrode from the first internal gate electrode; wherein the first and second control gate electrodes have individual sidewalls facing the semiconductor channel and the first and second conductive lines in a second direction transverse to the first direction
In re claim 2, Rajashekhar shows (fig. 5H) a second internal gate electrode (the other side, 54) spaced from the first internal gate electrode, wherein the second internal gate electrode overlies the first conductive line (42S) and underlies the second conductive line (42D), and wherein the individual sidewalls respectively face the first internal gate electrode and the second internal gate electrode.
In re claim 3, Rajashekhar shows (fig. 5H) a first gate dielectric layer (56) separating the semiconductor channel from the first internal gate electrode; and a second gate dielectric layer (the other 52) spaced from the first gate dielectric layer and separating the semiconductor channel from the second internal gate electrode.
In re claim 4, Rajashekhar shows (fig. 5H) a gate dielectric layer (56) between the semiconductor channel and the first internal gate electrode, wherein the gate dielectric layer has a continuous sidewall facing the first and second control gate electrodes (since 56 is also formed along the entire length of the control gate electrodes).
In re claim 5, Rajashekhar shows (fig. 5H) the first control gate electrode (66) and the first internal gate electrode (54) have individual widths extending in the first direction, and wherein the individual widths are different.
In re claim 7, Rajashekhar shows (fig. 5H) the second conductive line (42D) completely covers the first internal gate electrode (54) and the semiconductor channel (60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-18, as far as understood, are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al. (US Pub. 2021/0242241 A1) in view of Dong et al. (US Pub. 2019/0304986 A1).
In re claim 15, Rajashekhar shows (fig. 5H) a memory device, comprising: a first source/drain region (42S) and a second source/drain region (42D) overlying the first
source/drain region; layer. Dong et al. discloses (fig. 1D) a semiconductor memory in which a blocking dielectric layer (128) comprises a ferroelectric, which is equivalent to an oxide and suitable for use in a memory device. Therefore, it would have been obvious to one of ordinary skill in the art at the time filing to modify the device of Rajashekhar by forming the dielectric layer of ferroelectric because Dong teaches that such materials are equivalent and suitable for use in memory devices.
In re claim 16, when Rajashekhar and Dong are combined, the prior art shows all of the elements of the claims including a second control gate electrode (other side of 66; Rajashekhar, fig. 5H) and a second ferroelectric layer (from Dong) between and bordering the second control gate electrode and another one of the individual internal gate electrodes (other side of 54).
In re claim 17, when Rajashekhar and Dong are combined, the prior art shows all of the elements of the claims. Rajashekhar shows (fig. 12A) a first conductive line (part of 9) underlying the first control gate electrode; a second conductive line (not shown, but must be present to provide interconnection) overlying the second control gate electrode, wherein the first and second conductive lines are elongated in parallel; and a pair of conductive vias (88) extending respectively from the first and second conductive lines respectively to the first and second control gate electrodes.
In re claim 18, when Rajashekhar and Dong are combined, the prior art shows all of the elements of the claims. Rajashekhar shows (fig. 5H) a continuous dielectric layer (56) overlying the first source/drain region and underlying the second source/drain region, wherein the first and second CIS structures comprises individual portions of the continuous dielectric layer, which separate the continuous semiconductor layer respectively from the individual internal gate electrodes.
Allowable Subject Matter
Claims 6, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Although the claims are rejected above under 35 USC 112, the claims contains allowable subject matter. If the 112 Rejection is overcome, the claims would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-14 are allowed.
In re claim 8, the following is an examiner’s statement of reasons for allowance: the prior art references, alone or in combination, do not show a memory device, comprising: a first conductive structure and a second conductive structure overlying the first conductive structure; a first gate electrode and a semiconductor layer vertically between the first and second conductive structures, wherein the semiconductor layer extends from the first conductive structure to the second conductive structure; a gate dielectric layer laterally between and bordering the first gate electrode and the semiconductor layer; a second gate electrode having a height greater than a height of the semiconductor layer; and a ferroelectric layer between and bordering the first and second gate electrodes; wherein the semiconductor layer overlies the first gate electrode and underlies the first gate electrode.
The closest prior art reference is Rajashekhar et al. (US Pub. 2021/0242241 A1). Rajashekhar shows various elements of the claims including the first and second conductive structures, a first gate electrode and a semiconductor layer vertically between the first and second conductive structures, a gate dielectric layer laterally between and bordering the first gate electrode and the semiconductor layer; a second gate electrode having a height greater than a height of the semiconductor layer. However, Rajashekhar does not specifically disclose the semiconductor layer overlies the first gate electrode and underlies the first gate electrode.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Petti (US Pub. 2023/0077181 A1), Lai (US Pub. 2021/0126013 A1), Morris (US Pub. 2020/0105773 A1), Lue (US Pub. 2017/0194340 A10, Yoo (KR-20190036077-A), Okita (JP-2018037441-A) and Kang (CN-105304638-A) also disclose elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815
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