Prosecution Insights
Last updated: August 17, 2026
Application No. 18/422,479

MEMORY DEVICE WITH FLAT-TOP BOTTOM ELECTRODES AND METHODS FOR FORMING THE SAME

Final Rejection §102§112
Filed
Jan 25, 2024
Priority
Jan 15, 2020 — divisional of 11/437,431 +1 more
Examiner
MILLER, JAMI VALENTINE
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1036 granted / 1092 resolved
+26.9% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
24 currently pending
Career history
1106
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
31.0%
-9.0% vs TC avg
§102
41.7%
+1.7% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application Acknowledgement is made of the amendment received 4/14/26. Claims 1-4, 7-13 and 19-27 are pending in this application. Claims 1-2, 7-9 and 19-25 were amended, claims 5-6, and 14-18 were cancelled in the amendment received 4/14/26. Response to Arguments Applicant's arguments filed 4/14/26 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 112 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 19, 20 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claims 19 recites the limitation “wherein a width of the bottom electrode and a width of the bottom connection structure are longer than a width of the memory element”. It is unclear what is meant by wherein a width of the bottom electrode and a width of the bottom connection structure are longer than a width of the memory element. One reasonable interpretation is that the sum of the widths of the bottom electrode and the bottom connection structure combined is wider than that of the memory element. Another reasonable interpretation is that the width of the bottom electrode is wider than that of the memory element and the width of the bottom connection structure is also wider than that of the memory element. The limitation does not have well defined boundaries. One of ordinary skill in the relevant art would not know what structures/steps are covered by the limitation. For these reasons, the claim is indefinite. Claims 20 and 23 depend from rejected claim 119, include all limitations of claim 19 and therefore are rejected for the same reason. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-2, 8-10, 13, 19, 21-22 and 24-25 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Sung et al. (US Patent Application Publication No 2013/0026585) hereinafter referred to as Sung. Per Claim 1 Sung discloses a memory device, comprising (see figure 11) a bottom connection structure (14): and a memory cell (including 24/32/34/36), comprising: a bottom electrode (24) on the bottom connection structure, wherein a peripheral portion of the bottom electrode is disposed above a peripheral portion of the bottom connection structure; (as shown in figure 11) a memory element (32) on the bottom electrode (24); and dielectric structure (60) on a sidewall of the memory element and on an upper surface of the bottom electrode. (see figure 11) Per Claim 2 Sung discloses the device of claim 1, wherein the dielectric structure (60) comprises a sidewall spacer on the sidewall of the memory element and on the uppermost surface of the bottom electrode (as shown), wherein the peripheral portion of the bottom electrode extends beyond the sidewall spacer. (see figure 11) Per Claim 8 Sung discloses the device of claim 1, wherein the sidewall of the memory element comprises a tapered sidewall that is tapered in a direction away from the bottom electrode. (see figure 11) Per Claim 9 Sung discloses the device of claim 1, including: an etch stop layer (62) adjacent the dielectric structure (60) on the uppermost surface of the bottom electrode. (see figure 10-11) Per Claim 10 Sung discloses the device of claim 1, including where the memory element comprises a magnetic tunnel junction (32) comprising: a reference magnetization layer; a nonmagnetic tunnel barrier layer on the reference magnetization layer; and a free magnetization layer on the nonmagnetic tunnel barrier layer. (described in [0013]) Per Claim 13 Sung discloses the device of claim 1, including where the memory element further comprises a capping layer (44) on the free magnetization layer. (see [0017]) The examiner notes that the term "on" includes "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween) Per Claim 19 Sung discloses a memory device, comprising (see figure 1) a bottom connection structure (14): and a memory cell (including 24/32/34/36), comprising: a bottom electrode (24) on the bottom connection structure, (as shown in figure 11) a memory element (32) on an uppermost surface of the bottom electrode (24); and wherein a width of the bottom electrode (24) and a width of the bottom connection structure (14) are longer than a width of the memory element (32); (see figure 11) and dielectric structure (60) on a sidewall of the memory element and on the uppermost surface of the bottom electrode. (see figure 11) Per Claim 21 Sung discloses the device of claim 1, including a via-level dielectric layer (12), wherein the bottom connection structure (14) is in the via-level dielectric layer, and the bottom electrode (24) protrudes above a top surface of the via-level dielectric layer (as shown in figure 11) Per Claim 22 Sung discloses the device of claim 10, including where the memory cell further comprises a top electrode (34) disposed on the magnetic tunnel junction (32), the top electrode and magnetic tunnel junction include sloping sidewalls (as shown in figure 11), and the dielectric structure (60) is on the sloping sidewalls of the top electrode and the magnetic tunnel junction. (as shown in figure 11) Per Claim 24 Lee discloses a memory device, comprising (see figure 1) a bottom connection structure (14): and a memory cell (including 24/32/34/36), comprising: a bottom electrode (24) on the bottom connection structure, (as shown in figure 11) a memory element (32) on an uppermost surface of the bottom electrode (24); wherein the bottom electrode (24) and the bottom connection structure (14) extend horizontally from the memory element (see figure 11) and dielectric structure (60) on a sidewall of the memory element and on an upper surface of the bottom electrode. (see figure 11) Per Claim 25 Lee discloses the device of claim 24 including where the dielectric structure comprises a sidewall spacer (60) on the sidewall of the memory element and on the uppermost surface of the bottom electrode, wherein a peripheral portion of the bottom electrode (24) extends beyond the sidewall spacer (60). (see fig. 11) Allowable Subject Matter Claims 3-4, 7, 11-12, and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 and 23 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jami Valentine Miller/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jan 25, 2024
Application Filed
May 28, 2024
Response after Non-Final Action
Jan 23, 2026
Non-Final Rejection mailed — §102, §112
Apr 14, 2026
Response Filed
Jul 10, 2026
Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+3.9%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

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