DETAILED ACTION
This action is responsive to the application No. 18/422,572 filed on January 25, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Group I invention and Species 2 reading on Fig. 8 in the reply filed on 06/17/2026 is acknowledged. Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8-11, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo (US 2022/0352268).
Regarding Claim 1, Seo (see, e.g., Fig. 4), teaches a display device, comprising:
a first electrode PE1 disposed on a substrate 110 (see, e.g., pars. 0086, 0107);
a bank BNL disposed on the substrate 110 and including an opening exposing at least a portion of the first electrode PE1 (see, e.g., par. 0110);
light emitting elements LE disposed on the first electrode PE1 (see, e.g., par. 0092);
an insulating layer FOL disposed on the bank BNL to overlap the bank BNL in a plan view (see, e.g., pars. 0138-0139, 0142); and
a second electrode CE disposed on the insulating layer FOL and the light emitting elements LE (see, e.g., par. 0130).
Regarding Claim 2, Seo teaches all aspects of claim 1. Seo (see, e.g., Fig. 4), teaches that the light emitting elements LE do not overlap the insulating layer FOL in a plan view.
Regarding Claim 3, Seo teaches all aspects of claim 2. Seo (see, e.g., Fig. 4), teaches that the light emitting elements LE are not disposed on the bank BNL.
Regarding Claim 4, Seo teaches all aspects of claim 1. Seo (see, e.g., Fig. 4 and Annotated Fig. 5), teaches the bank BNL includes:
a first surface BS contacting the substrate 110;
a second surface TS facing the first surface BS; and
an outer surface SS extending from the first surface BS to the second surface TS, and the insulating layer FOL overlaps the second surface TS of the bank BNL and the outer surface SS of the bank BNL in a plan view.
Regarding Claim 6, Seo teaches all aspects of claim 4. Seo (see, e.g., Fig. 4), teaches:
a via layer PLL filling the opening (see, e.g., par. 0131),
wherein the second electrode CE is disposed on the insulating layer FOL, the via layer PLL, and the light emitting elements LE.
Regarding Claim 8, Seo teaches all aspects of claim 6. Seo (see, e.g., Fig. 4), teaches that the via layer PLL contacts the insulating layer FOL overlapping the outer surface SS of the bank BNL in a plan view.
Regarding Claim 9, Seo teaches all aspects of claim 4. Seo (see, e.g., Fig. 4 and Annotated Fig. 5), teaches that:
each of the light emitting elements LE includes a first end LE1 and a second end LE2 facing the first end LE1, the first end LE1 directly contacts the first electrode PE1, and
the second end LE2 directly contacts the second electrode CE.
Regarding Claim 10, Seo teaches all aspects of claim 9. Seo (see, e.g., Figs. 4, 6, and Annotated Fig. 5), teaches that:
each of the light emitting elements LE includes a second semiconductor layer SEM1, an active layer MQW, and a first semiconductor layer SEM2 different from the second semiconductor layer SEM1, which are sequentially stacked on each other in a third direction DR3,
the first end LE1 of each of the light emitting elements LE is adjacent to the second semiconductor layer SEM1 of each of the light emitting elements LE, and
the second end LE2 of each of the light emitting elements LE is adjacent to the first semiconductor layer SEM2 of each of the light emitting elements LE (see, e.g., pars. 0123-0129).
Regarding Claim 11, Seo teaches all aspects of claim 10. Seo (see, e.g., Figs. 4 and 6), teaches that:
the first semiconductor layer SEM2 of each of the light emitting elements LE is an n-type semiconductor layer (see, e.g., par. 0129), and
the second semiconductor layer SEM1 of each of the light emitting elements LE is a p-type semiconductor layer (see, e.g., par. 0123).
Regarding Claim 13, Seo teaches all aspects of claim 1. Seo (see, e.g., Figs. 4), teaches:
a light control layer 200 on the second electrode CE, wherein the light control layer 200 comprises (see, e.g., par. 0102):
a first light blocking pattern PW partitioning an emission area EA and a non-emission area NEA (see, e.g., par. 0150);
a wavelength conversion pattern QDL disposed between the first light blocking pattern PW, and overlapping the emission area EA in a plan view (see, e.g., par. 0149);
a second light blocking pattern BK disposed on the first light blocking pattern PW (see, e.g., par. 0112); and
color filters CF disposed on the wavelength conversion pattern QDL (see, e.g., par. 0112).
Allowable Subject Matter
Claims 5, 7 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814
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