Prosecution Insights
Last updated: October 01, 2026
Application No. 18/422,617

Anti-Reflective Layer for Protecting an N-Polar Group III-Nitride Semiconductor Structure

Final Rejection §103§112
Filed
Jan 25, 2024
Examiner
MULERO FLORES, ERIC MANUEL
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
60 granted / 72 resolved
+15.3% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
30 currently pending
Career history
106
Total Applications
across all art units

Statute-Specific Performance

§103
59.3%
+19.3% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 72 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicants’ amendments filed 7/14/2026 have been entered and considered. The amendments to claims 1, 4-5, 8, 12, 17, and 19-20 and the cancellation of claims 3 and 11 are acknowledged. Response to Arguments Applicant’s arguments, filed 7/14/2026, with respect to the rejection of claims 3 and 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamada. The method in Yamada performs epitaxial growth of the Group-III nitride semiconductor layer and then a silicon nitride film is formed by plasma enhanced chemical vapor deposition. The layers are not continuously formed, such that forming the organic anti-reflective layer as taught in Parikh would not go against how the Group-III nitride semiconductor layer and anti-reflective layer in Yamada are formed. Applicant’s arguments with respect to claim 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 4 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites an anti-reflective layer is of a thickness that reflects 3% to 6% of light. At most, the disclosure in para. 0082 establishes that the anti-reflective layer has a reflectivity greater than 3% in a thickness range from about 85nm to 130nm. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 2, 4-6, and 20 are rejected under 35 U.S.C. 103as being unpatentable over Yamada US 20120211761 A1 (hereinafter referred to as Yamada), in view of Lin, in view of Parikh et al. US 20120193677 A1 (hereinafter referred to as Parikh). Regarding claim 1, Yamada teaches A Group III-nitride semiconductor structure (“a semiconductor device” para. 0024 FIG. 2A-2I), comprising: a Group III-nitride layer (“semiconductor layer” made of GaN or AlGaN that includes “electron transit layer 21”, “spacer layer 22”, “electron supply layer 23”, and “cap layer 24” disposed on “substrate 10”, para. 0024-0025); an anti-reflective layer (“silicon nitride (SiN) film 61”, para. 0025 FIG. 2A. Silicon nitride is known to have anti-reflective properties that depend on the layer thickness and the wavelength of light, as evidenced in Furukawa et al US 20020048858 A1 para. 0016 and Hsu et al. US 6784081 B1 col 4 lines 1-9) on the Group III-nitride semiconductor structure; a photoresist layer on the anti-reflective layer (a photoresist is applied onto “silicon nitride film 61”, para. 0026); wherein the anti-reflective layer has a thickness in a range of about 85 nm to about 130 nm or has a thickness of about 175 nm or greater (“silicon nitride (SiN) film 61” has a thickness of 200nm, para. 0025). However, Yamada fails to teach an N-Polar Group III-nitride semiconductor structure, an N-polar Group III-nitride semiconductor layer, the anti-reflective layer comprising an organic anti-reflective layer. Nevertheless, Li teaches that N-polar GaN and GaAlN transistors have superior performance, including lower dynamic on-resistance and higher breakdown voltage in HEMT devices compared to the Ga-polar transistors (Li para. 0003). The crystal structure in Yamada is not specified. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming the Group-III nitride semiconductor structure with N-polar orientation will improve the electrical performance of the device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Group III-nitride semiconductor structure in Yamada with the N-polar crystal orientation taught in Li. An N-polar Group III-nitride semiconductor structure has a dynamic on-resistance and breakdown voltage that is favorable for HEMT devices. However, Yamada in view of Lin, fails to teach wherein the anti-reflective layer comprises an organic anti-reflective layer. Nevertheless, Parikh teaches wherein the anti-reflective layer comprises an organic anti-reflective layer (“dielectric insulating layer 31” may be the organic materials polyimide or benzocyclobutene, para. 0030 FIG. 3). Yamadaand Parikh teach Group-III nitride HEMT devices. Makabe suggests silicon nitride as an insulator for the device while Parikh teaches that the “dielectric insulating layer 31” can be silicon nitride, polyimide, benzocyclobutene, or other inorganic or organic materials. Polyimides can have indices of refraction around 1.58-1.74 as seen in Table II, page 580, of “Optical Properties of Polyimide Thin Films. Effect of Chemical Structure and Morphology” by Lee et al., such that the examiner understands light is transmitted through or reflected depending on the incident angle of light. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon nitride and polyimide are materials suitable for use as an anti-reflective insulating layer on a HEMT device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the N-Polar Group III-nitride taught between Yamada and Lin with the organic material taught in Parikh. Organic materials are also suitable for use as anti-reflective insulating layers in HEMT devices. Regarding claim 2, Yamada, modified by Lin and Parikh, teaches wherein the anti-reflective layer has a thickness in a range of about 175 nm to about 400 nm (“silicon nitride (SiN) film 61” has a thickness of 200nm, para. 0025). Regarding claim 4, Yamada, modified by Lin and Parikh, teach the N-Polar Group III-nitride semiconductor structure of claim 1 but fail to teach wherein the anti-reflective layer has a thickness associated with a reflectivity of about 3% to about 6%. Nevertheless, it is known that anti-reflective layers are used to prevent reflection back onto the photoresist that cause patterning irregularities (see Abdallah et al. US 20090162800 A1 para. 0005, Xiang et al. US 20080176165 A1 para. 0005 and Hwang et al. US 20040014322 A1 para. 0002-0003). Abdallah also suggests in para. 0035 that the optimal thicknesses depend on the exposure wavelength. By reducing reflection, the photolithography is more precise and uniform. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that lower back reflection is desirable for achieving higher quality photolithography. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose thickness values of the antireflective layer in Abdallah based on the desired amount of antireflection. The less it reflects, the less defects are formed on the photoresist pattern. Regarding claim 5, Yamada, modified by Lin and Parikh, teaches the N-Polar Group III-nitride semiconductor structure of claim 1, wherein the N-Polar Group III-nitride semiconductor structure comprise the N-polar Group III-nitride layer (the GaN semiconductor layer in Yamada now modified to be N-Polar) provided on a substrate (“substrate 10” para. 0020). Regarding claim 6, Yamada, modified by Lin and Parikh, teaches the N-Polar Group III-nitride semiconductor structure of claim 5, wherein the substrate comprises silicon carbide (“substrate 10” is made of silicon carbide, para. 0021). Regarding claim 20, Yamada teaches A method for processing a Group III-nitride semiconductor structure (“a method for producing a semiconductor device” para. 0024 FIG. 2A-2I), comprising: providing an anti-reflective layer (“silicon nitride (SiN) film 61”, para. 0025 FIG. 2A. Silicon nitride is known to have anti-reflective properties that depend on the layer thickness and the wavelength of light, as evidenced in Furukawa et al US 20020048858 A1 para. 0016 and Hsu et al. US 6784081 B1 col 4 lines 1-9) on a Group III-nitride semiconductor (“semiconductor layer” made of GaN or AlGaN that includes “electron transit layer 21”, “spacer layer 22”, “electron supply layer 23”, and “cap layer 24” disposed on “substrate 10”, para. 0024-0025), the Group III-nitride semiconductor structure comprising a Group III-nitride layer (“semiconductor layer” including “electron transit layer 21” to “cap layer 20”); providing a photoresist layer on the anti-reflective layer (a photoresist is applied onto “silicon nitride film 61”, para. 0026); and conducting a photolithography process on the Group III-nitride semiconductor structure to pattern the photoresist layer (“photoresist is exposed by an exposure apparatus and then developed to form the resist pattern 62”, para. 0026); wherein the anti-reflective layer has a thickness of from about 85 nm to about 130 nm or has a thickness greater than about 175 nm (“silicon nitride (SiN) film 61” has a thickness of 200nm, para. 0025). However, Yamada fails to teach an N-polar Group, the anti-reflective layer comprising an organic anti-reflective layer. Nevertheless, Li teaches that N-polar GaN and GaAlN transistors have superior performance, including lower dynamic on-resistance and higher breakdown voltage in HEMT devices compared to the Ga-polar transistors (Li para. 0003). The crystal structure in Yamada is not specified. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming the Group-III nitride semiconductor structure with N-polar orientation will improve the electrical performance of the device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Yamada with the N-polar crystal orientation taught in Li. An N-polar Group III-nitride semiconductor structure has a dynamic on-resistance and breakdown voltage that is favorable for HEMT devices. However, Yamada in view of Lin, fails to teach wherein the anti-reflective layer comprises an organic anti-reflective layer. Nevertheless, Parikh teaches wherein the anti-reflective layer comprises an organic anti-reflective layer (“dielectric insulating layer 31” may be the organic materials polyimide or benzocyclobutene, para. 0030 FIG. 3). Yamadaand Parikh teach Group-III nitride HEMT devices. Makabe suggests silicon nitride as an insulator for the device while Parikh teaches that the “dielectric insulating layer 31” can be silicon nitride, polyimide, benzocyclobutene, or other inorganic or organic materials. Polyimides can have indices of refraction around 1.58-1.74 as seen in Table II, page 580, of “Optical Properties of Polyimide Thin Films. Effect of Chemical Structure and Morphology” by Lee et al., such that the examiner understands light is transmitted through or reflected depending on the incident angle of light. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon nitride and polyimide are materials suitable for use as an anti-reflective insulating layer on a HEMT device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yamada and Lin with the organic material taught in Parikh. Organic materials are also suitable for use as anti-reflective insulating layers in HEMT devices. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada, modified by Lin and Parikh, as applied to claim 6, in view of Ren et al. US 20180182879 A1 (hereinafter referred to as Ren). Yamada, modified by Lin and Parikh, teaches the N-Polar Group III-nitride semiconductor structure of claim 6 but fails to teach wherein the substrate comprises a 4H-silicon carbide substrate. Nevertheless, Ren teaches wherein the substrate comprises a 4H-silicon carbide substrate (“substrate 21” preferably comprises 4H-SiC, para. 0012 FIG. 2). Yamada, modified by Lin and Parikh, and Ren teach group-III nitride HEMT devices. Though Makabe teaches the use of a silicon carbide substrate, Ren teaches that 4H-SiC substrates in particular have high thermal conductivity and a small lattice mismatch with GaN (para. 0012). A 4H-SiC substrate like “substrate 21” provides a good growth substrate for GaN layers and offers improved heat dissipation for the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the 4H-SiC “substrate 21” in Ren can be used for its GaN growth and heat dissipation capabilities. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the N-Polar Group III-nitride semiconductor structure taught between Yamada, Lin, and Parikh, with the 4H silicon carbide substrate in Ren. 4H silicon carbide provides a suitable growth substate for GaN and facilitates heat dissipation from the device. Claims 8-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Abdallah et al. US 20090162800 A1 (hereinafter referred to as Abdallah), in view of Makabe US 20190027577 A1 (hereinafter referred to as Makabe). Regarding claim 8, Abdallah teaches A method for processing a semiconductor structure (“process for imaging a photoresist film” on a substrate, para. 0009 and 0036), comprising: providing an anti-reflective layer on a semiconductor layer (“antireflective coating composition is coated on the substrate” para. 0036), the anti-reflective layer comprising an organic anti-reflective layer (the antireflective coating composition includes organic compounds such as, ethyl cellosolve, methyl cellosolve, methyl lactate, ethyl lactate, and others used alone or in combination para. 0032); providing a photoresist layer on the anti-reflective layer (“A film of photoresist is then coated on top of the uppermost siloxane antireflective coating” para. 0041); and conducting a photolithography process on the semiconductor layer to pattern the photoresist layer (“the photoresist is imagewise exposed”, “The exposed photoresist is then developed”, and then “The patterned substrate can then be dry etched”, para. 0044-0045); However, Abdallah fails to teach an N-polar Group III-nitride semiconductor, an N-polar Group III-nitride layer of the N-polar Group III-nitride semiconductor structure, conducting a photolithography process on the N-Polar Group III-nitride semiconductor structure, wherein the anti-reflective layer has a thickness outside an anti-reflective range associated with the photolithography process. Nevertheless, Abdallah teaches methyl lactate as a component in the antireflective layer. The antireflective layer is made with thickness ranging from 15-200nm (para. 0035). Applicant has admitted as prior art that antireflective layers with methyl lactate having a thickness from about 85-130nm and 175-400nm exhibits anti-reflective behavior outside the anti-reflective range associated for photoligraphic processes. Because the prior art teaches the material and conditions for the anti-reflective behavior as recited in applicants disclosure, the examiner understands the antireflective layer in Abdallah has a thickness outside an anti-reflective range associated with the photolithography process. However, Abdallah fails to teach an N-polar Group III-nitride semiconductor, an N-polar Group III-nitride layer of the N-polar Group III-nitride semiconductor structure, conducting a photolithography process on the N-Polar Group III-nitride semiconductor structure. Nevertheless, Makabe teaches an N-polar Group III-nitride semiconductor structure (“epitaxial substrate 1A", para. 0019 FIG. 1 and 5A), an N-polar Group III-nitride layer ("nitride semiconductor layer 11, a barrier layer 12, a channel layer 13, and an insulating film 14" para. 0019 FIG. 1 and 5A, where the top surface of "nitride semiconductor layer 11" is an N-polar surface, para. 0022) of the N-polar Group III-nitride semiconductor structure, conducting a photolithography process on the N-Polar Group III-nitride semiconductor structure (since photolithography involves patterning of a photoresist, it is understood that the photoresist is patterned so that "insulating film 14" can be patterned, para. 0038). Abdallah and Makabe teach photolithography processes. Abdallah teaches that their method can be applied to a range of substrates, including silicon, metal, ceramics, and Group III/V materials (0038). The use of the organic antireflective layer leads to a defect free uniformly coated photoresist film and prevents back reflection of light during photolithography, improving pattern quality (para. 0005-0007). Makabe teaches photolithography performed to pattern “epitaxial substrate 1A” but no use of an anti-reflective layer is suggested (Makabe para. 0038-0039). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the photolithography process in Abdallah can be applied to the “epitaxial substrate 1A” in Makabe to produce patterns with less defects. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Abdallah with the N-Polar Group III-nitride semiconductor structure in Makabe. The photolithography process using the antireflective layer can be applied to the N-Polar Group III-nitride semiconductor structure to achieve a pattern with improved quality. Regarding claim 9, Abdallah, modified by Makabe, teach the method of claim 8, wherein the anti-reflective layer has a thickness of from about 85 nm to about 130 nm (antireflective layer thickness ranges from 15 nm to about 200 nm, Abdallah para. 0035). Regarding claim 10, Abdallah, modified by Makabe, teach the method of claim 9, wherein the anti-reflective layer has a thickness of from about 90 nm to about 110 nm (antireflective layer thickness ranges from 15 nm to about 200 nm, Abdallah para. 0035). Regarding claim 12, Abdallah, modified by Makabe, teach the method of claim 8, wherein the anti-reflective layer has thickness associated with a reflectivity of about 3% to 6%. Nevertheless, it is known that anti-reflective layers are used to prevent reflection back onto the photoresist that cause patterning irregularities (see Abdallah para. 0005, as well as Xiang et al. US 20080176165 A1 para. 0005 and Hwang et al. US 20040014322 A1 para. 0002-0003). Abdallah also suggests in para. 0035 that the optimal thicknesses depend on the exposure wavelength. By reducing reflection, the photolithography is more precise and uniform. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that lower back reflection is desirable for achieving higher quality photolithography. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose thickness values of the antireflective layer in Abdallah based on the desired amount of antireflection. The less it reflects, the less defects are formed on the photoresist pattern. Regarding claim 13, Abdallah, modified by Makabe, teach the method of claim 8, wherein the N-Polar Group III-nitride semiconductor structure comprises the N-polar Group III-nitride layer provided on a substrate (N-polar “nitride semiconductor layer 11” is on “support substrate 10”, para. 0021). Regarding claim 14, Abdallah, modified by Makabe, teach the method of claim 13, wherein the substrate comprises silicon carbide (“support substrate 10” is made of silicon carbide, para. 0021). Regarding claim 15, Abdallah, modified by Makabe, teach the method of claim 8, wherein conducting a photolithography process on the N-Polar Group III-nitride semiconductor structure to pattern the photoresist layer, comprises: exposing the photoresist layer to radiation to pattern the photoresist layer (“the photoresist is imagewise exposed” Abdallah para. 0044); and developing the photoresist layer to form a photoresist pattern (“The exposed photoresist is then developed in an aqueous developer to remove the treated photoresist” para. 0044). Regarding claim 16, Abdallah, modified by Makabe, teach the method of claim 15, comprising etching the anti-reflective layer and the N-polar Group III-nitride layer according to the photoresist pattern (“The patterned substrate can then be dry etched with an etching gas or mixture of gases, in a suitable etch chamber to remove the exposed portions of the antireflective film, with the remaining photoresist acting as an etch mask” Abdallah para. 0045. Also, “The antireflective coating in the exposed area is then typically dry etched using various etching gases, and the photoresist pattern is thus transferred to the substrate” para. 0005). Regarding claim 17, Abdallah, modified by Makabe, teach the method of claim 16, comprising removing the photoresist layer from the N-Polar Group III-nitride semiconductor structure (although Abdallah only teaches the photolithography process up to the etching of the substrate, Makabe shows there is no photoresist after the patterning in FIG. 5B. The photoresist used in the photolithography process is understood to be removed.) Regarding claim 19, Abdallah, modified by Makabe, teach the method of claim 8, comprising fabricating a semiconductor device on the N-polar Group III-nitride layer ("source and drain electrodes, 22 and 23" are formed into the "nitride semiconductor layer 11" and the "HEMT 2A" includes the "nitride semiconductor layer 11", Makabe para. 0038). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Abdallah, modified by Makabe, as applied to claim 17 above, in view of Hsiao 6444584 B1 (hereinafter referred to as Hsiao). Abdallah, modified by Makabe, teach the method of claim 17 but fail to teach removing any remaining anti-reflective layer from the N-Polar Group III-nitride semiconductor structure. Nevertheless, Hsiao US teaches the patterning of a semiconductor stack through use of a “patterned photoresist layer 20”; the stack includes an “organic anti-reflective coating 18” on a “blanket second silicon layer 16”, “blanket silicon containing dielectric layer 14” and “blanket first silicon layer 12” that is subsequently patterned into “patterned organic anti-reflective coating layer 18a”, “patterned second silicon layer 16a”, a “patterned silicon containing dielectric layer 14a” and a “patterned first silicon layer 12a” (col 6 lines 47-56). The “patterned photoresist layer 20” and “patterned organic anti-reflective layer 18a” are then removed (col 7 lines 27-30). The “organic anti-reflective coating 18” is used to attenuate radiation during the exposure of the photoresist (col 6 lines 1-20). Since it is removed, it is understood that “patterned organic anti-reflective coating 18a” was not meant to be part of the final stack structure. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the antireflective layer taught in Abdallah can be removed after patterning the “epitaxial substrate 1A” in Makebe so it is not part of the final structure. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Abdallah and Makebe with the removal step taught in Hsiao Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Jan 25, 2024
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §103, §112
Jul 06, 2026
Applicant Interview (Telephonic)
Jul 06, 2026
Examiner Interview Summary
Jul 14, 2026
Response Filed
Sep 09, 2026
Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+16.4%)
3y 3m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
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