DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgment has been made to the amendments received on 06/30/2026. Claims 1-13, 15, 17-21 and 43 are pending in this application. Claims 14, 16, 22-42 and 44-63 are previously cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9, 11, 13, 15, 17, 21 and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Allen et al (US 20040159865A1) in view of Colinge et al (US 20160071977A1).
Re claim 1 Allen teaches, a semiconductor device (fig 3B) comprising:
a semiconductor structure (10, fig 3B) [0058] comprising silicon carbide [0058];
a mesa structure (mesa, fig 3B) [0061] protruding in a first direction (vertical) from the semiconductor structure, the mesa structure extending in a second direction (lateral) between a first contact (20, fig 3B) [0060] on the semiconductor structure and a second contact (22, fig 3B) [0060] on the semiconductor structure [0075, 0076];
a channel region (14, fig 3B) [0036] in the mesa structure (mesa, fig 3B) [0061];
an electrically floating confining region (13, fig 3B) [0064] (not connected to an external voltage neutral or ground), the electrically floating confining region (13, fig 3B) [0064] in contact with the channel region (14, fig 3B) in the mesa structure; and
a third contact (40, fig 3B) [0064].
Allen does not teach the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the third contact on at least a portion of two or more of the top surface and the plurality of side surfaces of the mesa structure.
Colinge teaches the channel region (108, fig 2, 8) [0032] being bound by a top surface of the mesa structure (top of 108/106, fig 2, 8) and a plurality of side surfaces of the mesa structure (left/right surfaces of 108/106, fig 2, 8); and the third contact (302, fig 2, 8) [0028] on at least a portion (top portion of 108, fig 8) of two or more of the top surface (see fig 7) and the plurality of side surfaces of the mesa structure (left/right sides of 108, fig 7) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Colinge into the structure of Allen to include the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the third contact on at least apportion of two or more of the top surface and the plurality of side surfaces of the mesa structure as claimed.
The ordinary artisan would have been motivated to modify Allen based on the teaching of Colinge in the above manner for the purpose of improving the integration density of variety of electronic components [0002].
Re claim 2 Allen in view of Colinge teaches, the semiconductor device of claim 1, wherein the third contact (40, fig 3B) is between the first contact (20, fig 3B) and the second contact (22,fig 3B) [Allen 0061].
Re claim 3 Allen in view of Colinge teaches the semiconductor device of claim 1, wherein the third contact (40, fig 3B) is on a first sidewall (right sidewall see fig above) of the mesa structure and on a second sidewall (left sidewall) of the mesa structure [Allen 0064].
Re claim 4 Allen in view of Colinge teaches, the semiconductor device of claim 1, the third contact (40, fig 3B) is a Schottky contact with the mesa structure [Allen, 0075-0076].
Re claim 9 Allen in view of Colinge teaches, the channel region (14, fig 3B) has a first conductivity type (n-type) [Allen, 0062].
Re claim 11 Allen in view of Colinge teaches the semiconductor device of claim 1, wherein the electrically floating confining region (13, fig 3B) [Allen, 0064] is in the mesa structure (see fig above) [Allen, 0062].
Re claim 13 Allen in view of Colinge teaches, the semiconductor device of claim 1, wherein the channel region (14, fig 3B) provides an electrically conductive channel [0036] between the first contact (20, fig 3B) and the second contact (22, fig 3B) based on a voltage applied to the third contact (40, fig 3B) [Allen, 0036].
Re claim 15 Allen in view of Colinge teaches the semiconductor device of claim 1, the semiconductor structure comprises a semi-insulating silicon carbide substrate (10, fig 3B) [Allen, 0083].
Re claim 17 Allen in view of Colinge teaches the semiconductor device of claim 1, wherein the semiconductor device comprises a MESFET type FinFET device [Allen, 0064].
Re claim 21 Allen teaches a semiconductor device (fig 3B), comprising:
a semiconductor structure (10, see annotated fig above) [Allen, 0058] comprising silicon carbide [0058];
a source contact (20, fig 3B) [0060] on the semiconductor structure;
a drain contact (22, fig 3B) [0060] on the semiconductor structure;
a mesa structure (mesa, fig 3B) [0061] protruding from the semiconductor structure, the mesa structure comprising silicon carbide (mesa, fig 3B) [0061], the mesa structure comprising a channel region (14, fig 3B) [0036, 0064] and a confining region (13, fig 3B)[0064]; and
a gate contact (40, fig 3B) [0064].
Allen does not teach the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the gate contact on at least a portion of two or more of the top surface and the plurality of side surfaces of the mesa structure.
Colinge teaches the channel region (108, fig 2, 8) [0032] being bound by a top surface of the mesa structure (top of 108/106, fig 2, 8) and a plurality of side surfaces of the mesa structure (left/right surfaces of 108/106, fig 2, 8); and the gate contact (302, fig 2, 8) [0028] on at least a portion (top portion of 108, fig 8) of two or more of the top surface (see fig 7) and the plurality of side surfaces of the mesa structure (left/right sides of 108, fig 7) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Colinge into the structure of Allen to include the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the gate contact on at least apportion of two or more of the top surface and the plurality of side surfaces of the mesa structure as claimed.
The ordinary artisan would have been motivated to modify Allen based on the teaching of Colinge in the above manner for the purpose of improving the integration density of variety of electronic components [0002].
Re claim 43 Allen teaches, a lateral transistor device (fig 3B), comprising:
a semiconductor structure (10, see fig 3B) comprising silicon carbide [0058].
a mesa structure (mesa, see fig 3B) [0061] protruding from the semiconductor structure (see fig 3B), the mesa structure comprising silicon carbide (11/13/14, fig3B, comprising silicon carbide) [0086-0087].
the mesa structure comprising a channel region (14, fig 3B) [0036, 0061],
a gate contact (40, fig 3B) [0064].
Allen does not teach the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the gate contact on at least a portion of two or more of the top surface and the plurality of side surfaces of the mesa structure.
Colinge teaches the channel region (108, fig 2, 8) [0032] being bound by a top surface of the mesa structure (top of 108/106, fig 2, 8) and a plurality of side surfaces of the mesa structure (left/right surfaces of 108/106, fig 2, 8); and the gate contact (302, fig 2, 8) [0028] on at least a portion (top portion of 108, fig 8) of two or more of the top surface (see fig 7) and the plurality of side surfaces of the mesa structure (left/right sides of 108, fig 7) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Colinge into the structure of Allen to include the channel region being bound by a top surface of the mesa structure and a plurality of side surfaces of the mesa structure; and the gate contact on at least apportion of two or more of the top surface and the plurality of side surfaces of the mesa structure as claimed.
The ordinary artisan would have been motivated to modify Allen based on the teaching of Colinge in the above manner for the purpose of improving the integration density of variety of electronic components [0002].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Allen modified by Colinge applied to claim 1 and above further in view of Ward et al (US20070001176A1).
Re claim 5 Allen in view of Collinge teach, the semiconductor device of claim 1,
Allen and Colinge do not teach a dielectric layer between the third contact and the mesa structure.
Ward teaches a dielectric layer (36, fig 3) [0033] between the third contact (35, fig 3) [0033] and the mesa structure (mesa-type orientation, fig 3) [0032].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ward into the structure of Allen and Colinge to include a dielectric layer between the third contact and the mesa structure as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge based on the teaching of Ward in the above manner for the purpose to reduce the leakage current
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Allen modified by Colinge as applied to claim 1 and further in view of Sheppard et al (US 20010017370 A1)
Re claim 7 Allen in view of Colinge teach, the semiconductor device of claim 1,
Allen and Colinge do not teach the semiconductor device comprises a plurality of mesa structures, each mesa structure separated from an adjacent mesa structure by a recess
Sheppard does teach the semiconductor device comprises a plurality of mesa structures (plurality of mesa in fig 1) [0040], each mesa structure separated from an adjacent mesa structure by a recess (recess between each mesa, fig 1) [0040].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Sheppard to include the semiconductor device comprises a plurality of mesa structures, each mesa structure separated from an adjacent mesa structure by a recess as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge in the above manner so, Improve the efficiency of the device [0009].
Re claim 8. Allen in view of Colinge and Sheppard teaches the semiconductor device of claim 7,
wherein the third contact (see fig 1) on the semiconductor structure in the recess (recess fig 1) [Sheppard 0040].
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Allen modified by Colinge as applied to claim 9 and further in view of Singh et al (US 6218254B1).
Re claim 10 Allen in view of Colinge teaches the semiconductor device of claim 9, the electrically floating confining region (13, fig 3B) [0064] has a second conductivity type (p-type) [0064].
Allen and Colinge do not teach, wherein the electrically floating confining region is in the semiconductor structure, wherein the mesa structure at least partially overlaps the confining region.
Singh teaches the electrically floating confining region (layer 4, fig 9) [col 5, lines 56-59] is in the semiconductor structure (see fig 9) [col 8, lines 52-58] wherein the mesa structure (see fig 9) at least partially overlaps the confining region (layer 4, see fig 9) [col 5, lines 56-59].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Singh into the structure of Allen and Colinge to the electrically floating confining region is in the semiconductor structure, wherein the mesa structure at least partially overlaps the confining region as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge based on the teaching of Singh in the above manner doing so enables the production of devices which operate at higher frequencies. [col 7 line 55].
Re claim 12 Allen in view of Colinge teach semiconductor device of claim 1, the electrically floating confining region (13, fig 3B) [0064] is in the mesa (see fig3B).
Allen and Colinge does not teach the electrically floating confining region is in the semiconductor structure.
Singh does teach the electrically floating confining region (layer 4, fig 9) [col 8, lines 53-58 ] is in the semiconductor structure (see fig 3B) [col 8, lines 52-56].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Allen and Colinge into the structure of Singh to include the electrically floating confining region is in the semiconductor structure as claimed.
The ordinary artisan would have been motivated to modify Allen and Coligne based on the teaching of Singh in the above manner doing so enables the production of devices which operate at higher frequencies. [col 7 line 55].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Allen modified by Colinge as applied to claim 1 and further in view of Suzuki et al (US 20160247910 A1).
Re claim 18 Allen in view of Coligne teach the semiconductor device of claim 1,
Allen and Colinge does not teach the semiconductor device of claim 1, wherein the semiconductor device comprises a MOSFET type FinFET device.
Suzuki teaches the semiconductor device of claim 1, wherein the semiconductor device comprises a MOSFET type FinFET device (fig 1) [0008, 0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Suzuki into the structure of Allen to include the semiconductor device comprises a MOSFET type FinFET device as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge based on the teaching of Suzuki in the above manner for the purpose of an increase of an on-state resistance is reduced [0008].
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Allen modified by Colinge as applied to claim 1 in view of Noori et al (US 20210313293A1).
Re claim 19 Allen in view of Colinge teach the semiconductor device of claim 1,
Allen and Colinge do not teach the semiconductor device is part of an RF amplifier circuit.
Noori teaches the semiconductor device (fig 2A) is part of an RF amplifier circuit (200, fig 2A) [0091].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Noori into the structure of Allen and Colinge to include the semiconductor device is part of an RF amplifier circuit as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge based on the teaching of Noori in the above manner for the purpose of improving connection possibilities and better thermal performance [0127].
Re claim 20 Allen in view of Colinge teach the semiconductor device of claim 19,
Allen does not teach the RF amplifier circuit is associated with an operating frequency in a range of about 10 GHz to about 40 GHz.
Noori does teach the RF amplifier circuit (200, fig 2A) [0091] is associated with an
operating frequency in a range of about 10 GHz to about 40 GHz. (40-75 GHz) [0003].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Noori into the structure of Allen and Colinge to include the RF amplifier circuit is associated with an operating frequency in a range of about 10 GHz to about 40 GHz. as claimed.
The ordinary artisan would have been motivated to modify Allen and Colinge based on the teaching of Noori in the above manner for the purpose of improving connection possibilities and better thermal performance [0127].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936(Fed.Cir, 1990).
Response to Arguments
Applicant’s arguments with respect to claims 1-13, 15, 17-21 and 43 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tang et al (US20150031181A1) teaches a finfet is formed having a fin with a source region, a drain region, and a channel region between the source and drain region. Wu et al (US20190198672A1) teaches fabricating a Fin FET include providing a substrate having a fin structure
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 8/5/26
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