CTNF 18/423,215 CTNF 92123 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 2. Applicant’s election without traverse of Species A, identified as encompassing claims 1-4, 9-13, 15-17, and 21-28 is acknowledged. Note by the Examiner 3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis. Claim Objections 07-29-01 AIA 4. Claim s 1-4 and 21-24 are objected to because of the following informalities: Claim 1 lines 3 recites “the substrate” which should be changed to “the base layer”. All claims depending on the current claim incorporate the same issue . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 5. Claims 1-3, 9, and 15 are rejected under 35 U.S.C. 103 as obvious over Chang (US 2022/0352119 A1), hereinafter as C1, in view of Huang et al. (US 2014/0367777 A1), hereinafter as H1 PNG media_image1.png 865 1519 media_image1.png Greyscale PNG media_image2.png 922 1021 media_image2.png Greyscale 6. Regarding Claim 1 , C1 discloses a semiconductor structure (see in particular Figs. 1-2, 4, “Labeled Fig. 1” above, “Labeled Fig. 2” above, and [0027] “semiconductor substrate”) comprising: a base layer (element 201 of a central die, see [0030] “substrate 201”) having a front side (top side) and a back side (bottom side) ; a contact-to-transistor-component layer (element 103, see [0027] “individual devices (e.g., transistors, capacitors, diodes, resistors, inductors, and the like) 102 are formed in and on a substrate 101” and [0028] “interlayer dielectric layer (ILD) 103 … Metal lines and vias 105 are formed in the IMD layers 104 to provide an electrical connection to devices 102”) formed over the front side of the substrate (see Figs. 1-2) ; a via-between-contact-and-metallization layer (labeled element “Via-Between-Contact-And-Metallization-Layer, comprising a lowermost layer of element 104, see [0028] “IMD layers 104”) formed over the contact-to-transistor-component layer (see Figs. 1-2) ; a front-side interconnect structure (layers of element 104 excluding the lowermost layer) formed over the via-between-contact-and-metallization layer (see Figs. 1-2) and comprising: a first metallization layer (labeled element “First Metallization Layer”, comprising a lowermost element 105 among the front-side interconnect structure, see [0028] “Metal lines and vias 105”) and a plurality of second metallization layers (labeled element “Second Metallization Layers”) , separated by a plurality of interconnection layers (labeled element “Interconnection Layers”) ; at least one front-side capacitor (a capacitor on the top side of the base layer, see [0027] “the die 10 includes a front-end-of-line (FEOL) representing a first portion of the fabrication of an integrated circuit (die), where individual devices (e.g., transistors, capacitors, diodes, resistors, inductors, and the like) 102 are formed in and on a substrate 101” Selected to have at least transistors, capacitors, inductors) ; and at least one front-side inductor (an inductor on the top side of the base layer, see [0027]) ; and a back-side interconnect structure (see Fig. 2 structure below the central element 201) formed on the back side of the base layer (see Fig. 1 and “Labeled Fig. 2” above, the dies are stacked such that the structure as seen in Fig. 1 is repeated) and comprising: a first buried metallization layer (labeled element “First Buried Metallization Layer”, buried in intermetal dielectric layers 104) and a plurality of second buried metallization layers (labeled element “Second Buried Metallization Layers”, buried in intermetal dielectric layers 104) , separated by a plurality of buried interconnection layer (labeled element “Buried Interconnection Layer”, buried in intermetal dielectric layers 104) ; at least one back-side capacitor (a capacitor on a bottom side of the base layer, which is on a top side of the die below the central die which comprises the base layer, and see [0027]) ; and at least one back-side inductor (an inductor on a bottom side of the base layer, which is on a top side of the die below the central die which comprises the base layer, and see [0027]) . C1 does not disclose at least one front-side capacitor formed in the second metallization layers; and at least one front-side inductor formed in the second metallization layers; and at least one back-side capacitor formed in the second buried metallization layers; and at least one back-side inductor formed in the second buried metallization layers. H1 discloses capacitors and inductors formed in second metallization layers (see Fig. 1A elements 1061, 1062 and [0033]). The capacitors and inductors formed in second metallization layers as taught by H1 is incorporated as the location of the capacitors and inductors formed in second metallization layers of C1, wherein the combination discloses at least one front-side capacitor formed in the second metallization layers; and at least one front-side inductor formed in the second metallization layers; and at least one back-side capacitor formed in the second buried metallization layers; and at least one back-side inductor formed in the second buried metallization layers (each of the stacked die of C1 incorporate the location of the capacitor and inductor such that the front side capacitor and inductor are formed above the base layer in the central die in the second metallization layers, and the back side capacitor and inductor are formed in the equivalent location for the lower die below the base layer). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with C1 because the combination allows for integrated passive devices (such as a capacitor and inductor) which can implement for example a filter function, and can be applicable to other systems integrated chips, such as CPU, MCU, multi-voltage power system, integrated chips, etc (see H1 [0038]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known passive element integration location for another to obtain predictable results (see H1 Fig. 1A). 7. Regarding Claim 2 , C1, H1 disclose the semiconductor structure of Claim 1, wherein the at least one front-side capacitor and the at least one front-side inductor are formed in a same one of the second metallization layers (see H1 Fig. 1A) . 8. Regarding Claim 3 , C1, H1 disclose the semiconductor structure of Claim 1, wherein the at least one back-side capacitor and the at least one back-side inductor are formed in a same one of the second buried metallization layers (see H1 Fig. 1A) . 9. Regarding Claim 9 , C1 disclose a semiconductor structure (see in particular Figs. 1-2, 4, “Labeled Fig. 1” above, “Labeled Fig. 2” above, and [0027] “semiconductor substrate”) comprising: a base layer (element 201 of a central die, see [0030] “substrate 201”) having a front side (top side) and a back side (bottom side) ; a front-side interconnect structure (layers of element 104 excluding the lowermost layer) formed over the front side of the base layer (see Figs. 1-2) and comprising: a first metallization layer (labeled element “First Metallization Layer”, comprising a lowermost element 105 among the front-side interconnect structure, see [0028] “Metal lines and vias 105”) and a plurality of second metallization layers (labeled element “Second Metallization Layers”) , separated by a plurality of interconnection layers (labeled element “Interconnection Layers”) ; and at least one passive element (a capacitor on the top side of the base layer, see [0027] “the die 10 includes a front-end-of-line (FEOL) representing a first portion of the fabrication of an integrated circuit (die), where individual devices (e.g., transistors, capacitors, diodes, resistors, inductors, and the like) 102 are formed in and on a substrate 101” Selected to have at least transistors, capacitors, inductors) ; and a back-side interconnect structure (see Fig. 2 structure below the central element 201) formed on the back side of the base layer (see Fig. 1 and “Labeled Fig. 2” above, the dies are stacked such that the structure as seen in Fig. 1 is repeated) and comprising: a first buried metallization layer (labeled element “First Buried Metallization Layer”, buried in intermetal dielectric layers 104) and a plurality of second buried metallization layers (labeled element “Second Buried Metallization Layers”, buried in intermetal dielectric layers 104) , separated by a plurality of buried interconnection layer (labeled element “Buried Interconnection Layer”, buried in intermetal dielectric layers 104) ; and at least one buried passive element (a capacitor on a bottom side of the base layer, which is on a top side of the die below the central die which comprises the base layer, and see [0027]) . C1 does not disclose the at least one passive element formed in the second metallization layers ; and the at least one buried passive element formed in the second buried metallization layers H1 discloses passive elements formed in second metallization layers (see Fig. 1A elements 1061, 1062 and [0033]). The passive elements formed in second metallization layers as taught by H1 is incorporated as the location of the passive elements formed in second metallization layers of C1, wherein the combination discloses the at least one passive element formed in the second metallization layers ; and the at least one buried passive element formed in the second buried metallization layers (each of the stacked die of C1 incorporate the location of the capacitor and inductor such that the front side capacitor and inductor are formed above the base layer in the central die in the second metallization layers, and the back side capacitor and inductor are formed in the equivalent location for the lower die below the base layer). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with C1 because the combination allows for integrated passive devices (such as a capacitor and inductor) which can implement for example a filter function, and can be applicable to other systems integrated chips, such as CPU, MCU, multi-voltage power system, integrated chips, etc (see H1 [0038]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known passive element integration location for another to obtain predictable results (see H1 Fig. 1A). 10. Regarding Claim 15 , C1 disclose a semiconductor structure (see in particular Figs. 1-2, 4, “Labeled Fig. 1” above, “Labeled Fig. 2” above, and [0027] “semiconductor substrate”) , comprising: a base layer (element 201 of a central die, see [0030] “substrate 201”) ; a front-side interconnect structure (layers of element 104 excluding the lowermost layer) formed over the base layer (see Figs. 1-2) and comprising: a first metallization layer (labeled element “First Metallization Layer”, comprising a lowermost element 105 among the front-side interconnect structure, see [0028] “Metal lines and vias 105”) and a plurality of second metallization layers (labeled element “Second Metallization Layers”) , separated by a plurality of interconnection layers (labeled element “Interconnection Layers”) ; and at least one front-side capacitor (a capacitor on the top side of the base layer, see [0027] “the die 10 includes a front-end-of-line (FEOL) representing a first portion of the fabrication of an integrated circuit (die), where individual devices (e.g., transistors, capacitors, diodes, resistors, inductors, and the like) 102 are formed in and on a substrate 101” Selected to have at least transistors, capacitors, inductors) ; and a back-side interconnect structure (see Fig. 2 structure below the central element 201) formed under the base layer (see Fig. 1 and “Labeled Fig. 2” above, the dies are stacked such that the structure as seen in Fig. 1 is repeated) and comprising: a first buried metallization layer (labeled element “First Buried Metallization Layer”, buried in intermetal dielectric layers 104) and a plurality of second buried metallization layers (labeled element “Second Buried Metallization Layers”, buried in intermetal dielectric layers 104) , separated by a plurality of buried interconnection layer (labeled element “Buried Interconnection Layer”, buried in intermetal dielectric layers 104) ; and at least one back-side capacitor (a capacitor on a bottom side of the base layer, which is on a top side of the die below the central die which comprises the base layer, and see [0027]) . C1 does not disclose the at least one front-side capacitor formed in the second metallization layers; the at least one back-side capacitor formed in the second buried metallization layers H1 discloses capacitors and inductors formed in second metallization layers (see Fig. 1A elements 1061, 1062 and [0033]). The capacitors and inductors formed in second metallization layers as taught by H1 is incorporated as the location of the capacitors and inductors formed in second metallization layers of C1, wherein the combination discloses the at least one front-side capacitor formed in the second metallization layers; the at least one back-side capacitor formed in the second buried metallization layers (each of the stacked die of C1 incorporate the location of the capacitor and inductor such that the front side capacitor and inductor are formed above the base layer in the central die in the second metallization layers, and the back side capacitor and inductor are formed in the equivalent location for the lower die below the base layer). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with C1 because the combination allows for integrated passive devices (such as a capacitor and inductor) which can implement for example a filter function, and can be applicable to other systems integrated chips, such as CPU, MCU, multi-voltage power system, integrated chips, etc (see H1 [0038]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known passive element integration location for another to obtain predictable results (see H1 Fig. 1A). 11. Claims 4, 10, and 16 are rejected under 35 U.S.C. 103 as obvious over Chang (US 2022/0352119 A1), hereinafter as C1, in view of Huang et al. (US 2014/0367777 A1), hereinafter as H1, in view of Chen et al. (US 2018/0122781 A1), hereinafter as C2 12. Regarding Claim 4 , C1, H1 disclose the semiconductor structure of Claim 1, wherein the at least one front-side capacitor comprises a capacitor (see C1 [0027] and H1 [0033]) ; and the at least one back-side capacitor comprises a capacitor (see C1 [0027] and H1 [0033]). C1, H1 do not explicitly disclose the front-side and back-side capacitor are metal-oxide-metal (MOM) capacitors. C2 discloses the dielectric material of the capacitors is an oxide such that the capacitor is a metal-oxide-metal (MOM) capacitor (see [0025] “The dielectric layer may comprise high-K dielectric materials, an oxide”). The oxide material for the capacitor dielectric material as taught by C2 is incorporated as oxide dielectric material for the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor dielectric material for another to obtain predictable results (see C2 [0025]). 13. Regarding Claim 10 , C1, H1 disclose the semiconductor structure of Claim 9, wherein the at least one passive element comprises a capacitor (see C1 [0027] and H1 [0033]) ; and the at least one buried passive element comprises a capacitor (see C1 [0027] and H1 [0033]) C1, H1 do not explicitly disclose the front-side and back-side capacitor are MOM capacitors. C2 discloses the dielectric material of the capacitors is an oxide such that the capacitor is a MOM capacitor (see [0025] “The dielectric layer may comprise high-K dielectric materials, an oxide”). The oxide material for the capacitor dielectric material as taught by C2 is incorporated as oxide dielectric material for the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor dielectric material for another to obtain predictable results (see C2 [0025]). 14. Regarding Claim 16 , C1, H1 disclose the semiconductor structure of Claim 15, wherein the at least one front-side capacitor comprises a capacitor (see C1 [0027] and H1 [0033]) and a back-side capacitor comprises a capacitor (see C1 [0027] and H1 [0033]) C1, H1 do not explicitly disclose the front-side and back-side capacitor are MOM capacitors. C2 discloses the dielectric material of the capacitors is an oxide such that the capacitor is a MOM capacitor (see [0025] “The dielectric layer may comprise high-K dielectric materials, an oxide”). The oxide material for the capacitor dielectric material as taught by C2 is incorporated as oxide dielectric material for the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor dielectric material for another to obtain predictable results (see C2 [0025]). 15. Claims 11-13 and 24-25 are rejected under 35 U.S.C. 103 as obvious over Chang (US 2022/0352119 A1), hereinafter as C1, in view of Huang et al. (US 2014/0367777 A1), hereinafter as H1, in view of Chen et al. (US 2018/0122781 A1), hereinafter as C2, in view of Polomoff et al. (US 2022/0406732 A1), hereinafter as P1 16. Regarding Claim 11 , C1, H1, C2 disclose the semiconductor structure of Claim 10, wherein at least one of the MOM capacitor comprises one capacitor unit having two metal electrodes separated by dielectric materials (see C2 [0025]) . C1, H1, C2 do not disclose wherein each metal electrode comprises fingers, and bus for interconnecting the fingers. P1 discloses wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) . The shape of the capacitors as taught by P1 is incorporated as a shape of the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 17. Regarding Claim 12 , C1, H1, C2, P1 disclose the semiconductor structure of Claim 11, wherein the MOM capacitor in the front-side interconnect structure is disposed in one of the second metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) ; and the MOM capacitor in the back-side interconnect structure is disposed in one of the second buried metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) . 18. Regarding Claim 13 , C1, H1, C2 disclose the semiconductor structure of Claim 10, wherein the MOM capacitor each comprises two or more capacitor units (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) , wherein the capacitor unit comprises two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]) . C1, H1, C2 do not explicitly disclose the two or more capacitor units stacking in the second metallization layers or the second buried metallization layers along a direction away from the base layer, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers P1 discloses two or more capacitor units stacking along a direction away from the substrate, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1, wherein the combination discloses stacking away from the base layer . It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 19. Regarding Claim 21 , C1, H1, C2 disclose the semiconductor structure of Claim 4, wherein at least one of the MOM capacitor comprises one capacitor unit having two metal electrodes separated by dielectric materials (see C2 [0025]). C1, H1, C2 do not disclose wherein each metal electrode comprises fingers, and bus for interconnecting the fingers. P1 discloses wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) . The shape of the capacitors as taught by P1 is incorporated as a shape of the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 20. Regarding Claim 22 , C1, H1, C2, P1 disclose the semiconductor structure of Claim 21, wherein the MOM capacitor in the front-side interconnect structure is disposed in one of the second metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) ; and the MOM capacitor in the back-side interconnect structure is disposed in one of the second buried metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) . 21. Regarding Claim 23 , C1, H1, C2 disclose the semiconductor structure of Claim 4, wherein the MOM capacitor each comprises two or more capacitor units in the second metallization layers (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) or the second buried metallization layers (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) along a direction away from the base layer, wherein the capacitor unit comprises two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]) . C1, H1, C2 do not explicitly disclose the two or more capacitor units stacking in the second metallization layers or the second buried metallization layers along a direction away from the base layer, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers P1 discloses two or more capacitor units stacking along a direction away from the substrate, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1, wherein the combination discloses stacking away from the base layer . It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 22. Regarding Claim 26 , C1, H1, C2 disclose the semiconductor structure of Claim 16, wherein at least one of the MOM capacitor comprises one capacitor unit (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062”) having two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]). C1, H1 do not explicitly disclose wherein each metal electrode comprises fingers, and bus for interconnecting the fingers. P1 discloses wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 23. Regarding Claim 27 , C1, H1, P1 disclose the semiconductor structure of Claim 26, wherein the MOM capacitor in the front-side interconnect structure is disposed in one of the second metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) ; and the MOM capacitor in the back-side interconnect structure is disposed in one of the second buried metallization layers (see H1 Fig. 1A elements 1061, 1062 and [0033]) . 24. Regarding Claim 28 , C1, H1, C2 disclose the semiconductor structure of Claim 16, wherein the MOM capacitor each comprises two or more capacitor units in the second metallization layers (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) or the second buried metallization layers (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) along a direction away from the base layer, wherein the capacitor unit comprises two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]) . C1, H1, C2 do not explicitly disclose the two or more capacitor units stacking in the second metallization layers or the second buried metallization layers along a direction away from the base layer, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers P1 discloses two or more capacitor units stacking along a direction away from the substrate, and wherein each metal electrode comprises fingers, and bus for interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1, wherein the combination discloses stacking away from the base layer . It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 25. Claims 17 and 24-25 are rejected under 35 U.S.C. 103 as obvious over Chang (US 2022/0352119 A1), hereinafter as C1, in view of Huang et al. (US 2014/0367777 A1), hereinafter as H1, in view of Polomoff et al. (US 2022/0406732 A1), hereinafter as P1 26. Regarding Claim 17 , C1, H1 disclose the semiconductor structure of Claim 15, wherein the at least one front-side capacitor comprises two or more front-side capacitors (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) and the at least one back-side capacitor comprises two or more back-side capacitors (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062” selected as more than one) . C1, H1 do not explicitly disclose the front-side capacitors are identical and the back-side capacitors are identical . P1 discloses identical inductors and capacitors (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “From level-to-level, these sections that are patterned into the shape(s) of electromagnetic device(s) can be essentially the same and vertically aligned”). The stacked identical inductors and capacitors as taught by P1 is incorporated as stacked identical inductors and capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 27. Regarding Claim 24 , C1, H1 disclose the semiconductor structure of Claim 1, wherein at least one of the at least one front-side capacitor and the at least one back-side capacitor comprises at least one capacitor unit (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062”) having two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]). C1, H1 do not explicitly disclose wherein at least one of the metal electrodes comprises a plurality of fingers and a bus interconnecting the fingers, wherein the fingers of the two metal electrodes are arranged in an alternating pattern. P1 discloses wherein at least one of the metal electrodes comprises a plurality of fingers and a bus interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) , wherein the fingers of the two metal electrodes are arranged in an alternating pattern (see Fig. 9E) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). 28. Regarding Claim 25 , C1, H1 disclose the semiconductor structure of Claim 9, wherein at least one of the at least one front-side capacitor and the at least one back-side capacitor comprises at least one capacitor unit (see C1 [0027] “capacitors … inductors” H1 [0033] “one or more capacitors 16061 and one or more inductor 16062”) having two metal electrodes separated by dielectric materials (see H1 Fig. 1A and [0033]) . C1, H1 do not disclose wherein at least one of the metal electrodes comprises a plurality of fingers and a bus interconnecting the fingers, wherein the fingers of the two metal electrodes are arranged in an alternating pattern. P1 discloses wherein at least one of the metal electrodes comprises a plurality of fingers and a bus interconnecting the fingers (see Fig. 9E and [0056] “metal wire patterns 322 of the first and second metallic barriers 325.1 and 325.2 at any given level”, [0057] “multi-finger capacitor plates of the capacitor”; the bus portion is the section of element 322 which connects to each of the fingers on each side) , wherein the fingers of the two metal electrodes are arranged in an alternating pattern (see Fig. 9E) The stacking direction of the two or more capacitor units and shape of the capacitors as taught by P1 is incorporated as a stacking direction of the two or more capacitor units and shape of the capacitors of C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with C1 because the combination allows for integrated passive circuitry in the interconnect layers which can be used for example as a band pass filter from level-to-level (see P1 [0057]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor structure implementation for another to obtain predictable results (see P1 Fig. 9E a planar capacitor instead of a vertical capacitor). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m.. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL PARK/Examiner, Art Unit 2818 Application/Control Number: 18/423,215 Page 2 Art Unit: 2818 Application/Control Number: 18/423,215 Page 3 Art Unit: 2818 Application/Control Number: 18/423,215 Page 4 Art Unit: 2818 Application/Control Number: 18/423,215 Page 5 Art Unit: 2818 Application/Control Number: 18/423,215 Page 6 Art Unit: 2818 Application/Control Number: 18/423,215 Page 7 Art Unit: 2818 Application/Control Number: 18/423,215 Page 8 Art Unit: 2818 Application/Control Number: 18/423,215 Page 9 Art Unit: 2818 Application/Control Number: 18/423,215 Page 10 Art Unit: 2818 Application/Control Number: 18/423,215 Page 11 Art Unit: 2818 Application/Control Number: 18/423,215 Page 12 Art Unit: 2818 Application/Control Number: 18/423,215 Page 13 Art Unit: 2818 Application/Control Number: 18/423,215 Page 14 Art Unit: 2818 Application/Control Number: 18/423,215 Page 15 Art Unit: 2818 Application/Control Number: 18/423,215 Page 16 Art Unit: 2818 Application/Control Number: 18/423,215 Page 17 Art Unit: 2818 Application/Control Number: 18/423,215 Page 18 Art Unit: 2818 Application/Control Number: 18/423,215 Page 19 Art Unit: 2818 Application/Control Number: 18/423,215 Page 20 Art Unit: 2818 Application/Control Number: 18/423,215 Page 21 Art Unit: 2818 Application/Control Number: 18/423,215 Page 22 Art Unit: 2818
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